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    Methods to Improve Leakage for ZrO2 Based High K MIM Capacitor
    31.
    发明申请
    Methods to Improve Leakage for ZrO2 Based High K MIM Capacitor 审中-公开
    改善ZrO2基高K MIM电容漏电的方法

    公开(公告)号：US20140183696A1

    公开(公告)日：2014-07-03

    申请号：US13737138

    申请日：2013-01-09

    Applicant: INTERMOLECULAR INC.

    Inventor： Xiangxin Rui ,  Mitsuhiro Horikawa ,  Hiroyuki Ode ,  Karthik Ramani

    IPC: H01L49/02

    CPC classification number: H01L28/40 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75

    Abstract: A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer.

    Abstract translation: 形成金属绝缘体金属（MIM）DRAM电容器的第一电极层，其中第一电极层包含导电基底层和导电金属氧化物层。 形成金属绝缘体金属（MIM）DRAM电容器的第二电极层，其中第二电极层包含导电基底层和导电金属氧化物层。 在一些实施例中，第一电极层和第二电极层都包含导电基底层和导电金属氧化物层。

    Methods to improve leakage of high K materials
    32.
    发明授权
    Methods to improve leakage of high K materials 有权
    改善高K材料泄漏的方法

    公开(公告)号：US08766346B1

    公开(公告)日：2014-07-01

    申请号：US13720289

    申请日：2012-12-19

    Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

    Inventor： Xiangxin Rui ,  Sergey Barabash

    IPC: H01L29/92 ,  H01L49/02

    CPC classification number: H01L28/75 ,  H01L28/40 ,  H01L28/56 ,  H01L28/60

    Abstract: A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capacitor stack including an oxygen donor layer inserted between the dielectric layer and at least one of the two electrode layers. In some embodiments, the dielectric layer may be doped with an oxygen donor dopant. The oxygen donor materials provide oxygen to the dielectric layer and reduce the concentration of oxygen vacancies, thus reducing the leakage current.

    Abstract translation: 降低DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括形成电容器堆叠，该电容器堆叠包括介于介电层和两个电极层中的至少一个之间的供氧体层。 在一些实施例中，介电层可以掺杂有氧供体掺杂剂。 氧供体材料为介电层提供氧气并降低氧空位的浓度，从而减少漏电流。

    Doped electrodes for DRAM applications
    33.
    发明授权
    Doped electrodes for DRAM applications 有权
    用于DRAM应用的掺杂电极

    公开(公告)号：US08569819B1

    公开(公告)日：2013-10-29

    申请号：US13915050

    申请日：2013-06-11

    Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

    Inventor： Xiangxin Rui ,  Hiroyuki Ode

    IPC: H01L27/108 ,  H01L29/94 ,  H01L21/8242 ,  H01L21/329

    CPC classification number: H01L28/65 ,  H01L28/40 ,  H01L28/60

    Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 μΩcm. Advantageously, the electrode layers are conductive molybdenum oxide.

    Abstract translation: 形成用于MIM DRAM电容器的金属氧化物第一电极层，其中第一和/或第二电极层含有一个或多个掺杂剂，直到总掺杂浓度，其将不会阻止电极层在随后的退火步骤期间结晶。 一种或多种掺杂剂具有大于约5.0eV的功函数。 一种或多种掺杂剂的电阻率小于约1000μOggacm。 有利地，电极层是导电性氧化钼。

    High performance dielectric stack for DRAM capacitor
    34.
    发明授权
    High performance dielectric stack for DRAM capacitor 有权
    用于DRAM电容器的高性能电介质堆叠

    公开(公告)号：US08546236B2

    公开(公告)日：2013-10-01

    申请号：US13738866

    申请日：2013-01-10

    Applicant: Intermolecular, Inc.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Mitsuhiro Horikawa ,  Kenichi Koyanagi ,  Hiroyuki Ode ,  Xiangxin Rui

    IPC: H01L21/20 ,  H01L21/31

    CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/75

    Abstract: A method for fabricating a DRAM capacitor stack is described wherein the dielectric material is a multi-layer stack formed from a highly-doped material combined with a lightly or non-doped material. The highly-doped material remains amorphous with a crystalline content of less than 30% after an annealing step. The lightly or non-doped material becomes crystalline with a crystalline content of equal to or greater than 30% after an annealing step. The dielectric multi-layer stack maintains a high k-value while minimizing the leakage current and the EOT value.

    Abstract translation: 描述了制造DRAM电容器堆叠的方法，其中电介质材料是由与轻掺杂或非掺杂材料组合的高掺杂材料形成的多层叠层。 在退火步骤之后，高掺杂材料保持无定形，结晶含量小于30％。 在退火步骤之后，轻掺杂或非掺杂材料变成结晶含量等于或大于30％的晶体。 电介质多层堆叠保持高的k值，同时使漏电流和EOT值最小化。

    Methods for depositing high-K dielectrics
    35.
    发明授权
    Methods for depositing high-K dielectrics 有权
    沉积高K电介质的方法

    公开(公告)号：US08541828B2

    公开(公告)日：2013-09-24

    申请号：US13668488

    申请日：2012-11-05

    Applicant: Intermolecular, Inc.

    Inventor： Imran Hashim ,  Edward L. Haywood ,  Sandra G. Malhotra ,  Xiangxin Rui ,  Sunil Shanker

    IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC classification number: H01L21/3141 ,  C23C16/02 ,  C23C16/405 ,  H01L21/02186 ,  H01L21/02271 ,  H01L21/02315 ,  H01L21/31604 ,  H01L28/91

    Abstract: Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer includes at least a portion of rutile titanium oxide.

    Abstract translation: 描述了用于沉积高K电介质的方法，包括在衬底上沉积第一电极，其中第一电极选自铂和钌，对暴露的金属施加氧等离子体处理以减小接触角 并且使用化学气相沉积工艺和原子层沉积工艺中的至少一种将氧化钛层沉积在暴露的金属上，其中氧化钛层包括至少一部分金红石型氧化钛。

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