公开(公告)号：US06800910B2

公开(公告)日：2004-10-05

申请号：US10335474

申请日：2002-12-31

申请人： Ming-Ren Lin ,  Jung-Suk Goo ,  Haihong Wang ,  Qi Xiang

发明人： Ming-Ren Lin ,  Jung-Suk Goo ,  Haihong Wang ,  Qi Xiang

IPC分类号： H01L27105

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

摘要： A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.

摘要翻译： FinFET器件采用应变硅来增强载流子迁移率。 在一种方法中，FinFET体从覆盖在电介质层上的硅锗层（SiGe）构图。 然后在硅锗FinFET体上形成硅的外延层。 由于本征硅和作为外延硅生长的模板的硅锗晶格的不同维度，在外延硅中引起应变。 与松弛硅相比，应变硅具有增加的载流子迁移率，结果外延应变硅在FinFET中提供增加的载流子迁移率。 因此，可以在采用应变硅沟道层的FinFET中实现更高的驱动电流。

公开(公告)号：US06797602B1

公开(公告)日：2004-09-28

申请号：US10071207

申请日：2002-02-11

申请人： George Jonathan Kluth ,  Qi Xiang

发明人： George Jonathan Kluth ,  Qi Xiang

IPC分类号： H01L213205

CPC分类号： H01L29/6653 ,  H01L21/268 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7834

摘要： Semiconductor devices, such as transistors, with a supersaturated concentration of dopant in the source/drain extension and metal silicide contacts enable the production of smaller, higher speed devices. Supersaturated source/drain extensions are subject to dopant diffusion out from the source/drain extension during high temperature metal silicide contact formation. The formation of lower temperature metal silicide contacts, such as nickel silicide contacts, prevents dopant diffusion and maintains the source/drain extensions in a supersaturated state throughout semiconductor device manufacturing.

摘要翻译： 在源极/漏极延伸和金属硅化物触点中具有过饱和浓度的掺杂剂的晶体管等半导体器件能够生产更小更高速度的器件。 在高温金属硅化物接触形成期间，过饱和源极/漏极延伸部分从源极/漏极延伸部分扩散出来。 低温金属硅化物接触（例如硅化镍接触）的形成防止掺杂剂扩散，并且在整个半导体器件制造过程中将源极/漏极延伸部保持在过饱和状态。

公开(公告)号：US06787423B1

公开(公告)日：2004-09-07

申请号：US10314331

申请日：2002-12-09

申请人： Qi Xiang

发明人： Qi Xiang

IPC分类号： H01L21336

CPC分类号： H01L29/1054 ,  H01L21/76232 ,  H01L29/0653

摘要： High-speed semiconductor devices with reduced source/drain junction capacitance and reduced junction leakage based on strain silicon technology are fabricated by extending a shallow trench isolation region under the strained silicon layer. Embodiments include anisotropically etching the trench region and subsequently isotropically etching the trench to form laterally extending regions under the strained silicon layer. Embodiments also include filling the trench with an insulating material such that an air pocket is formed in the trench.

摘要翻译： 通过在应变硅层下面扩展浅沟槽隔离区域，制造出具有较低源极/漏极结电容和基于应变硅技术的减少结漏电的半导体器件。 实施例包括各向异性蚀刻沟槽区域，随后各向同性蚀刻沟槽，以在应变硅层下方形成横向延伸的区域。 实施例还包括用绝缘材料填充沟槽，使得在沟槽中形成气穴。

公开(公告)号：US06764912B1

公开(公告)日：2004-07-20

申请号：US09919943

申请日：2001-08-02

申请人： John Clayton Foster ,  Eric N. Paton ,  Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser ,  Paul L. King

发明人： John Clayton Foster ,  Eric N. Paton ,  Matthew S. Buynoski ,  Qi Xiang ,  Paul R. Besser ,  Paul L. King

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L29/51 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656

摘要： The formation of metal silicides in silicon nitride spacers on a gate electrode causes bridging between a gate electrode and the source and drain regions of a semiconductor device. The bridging is prevented by forming a thin layer of silicon oxide on the silicon nitride spacers prior to forming the metal silicide layers on the device.

摘要翻译： 栅电极上的氮化硅间隔物中的金属硅化物的形成导致栅电极与半导体器件的源区和漏区之间的桥接。 通过在器件上形成金属硅化物层之前在氮化硅间隔物上形成氧化硅薄层来防止桥接。

公开(公告)号：US06743689B1

公开(公告)日：2004-06-01

申请号：US10341427

申请日：2003-01-14

申请人： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

发明人： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

IPC分类号： H01L21336

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/268 ,  H01L29/458 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621

摘要： Semiconductor devices comprising fully and partially depleted SOI transistors with accurately defined monocrystalline or substantially completely monocrystalline silicon source/drain extensions are fabricated by selectively pre-amorphizing intended source/drain extensions, ion implanting dopants into the pre-amorphized regions and laser thermal annealing to effect crystallization and activation of the source/drain extensions. Embodiments include forming a gate electrode over an SOI substrate with a gate dielectric layer therebetween, forming silicon nitride sidewall spacers on the side surfaces of the gate electrode, forming source/drain regions, forming a thermal oxide layer on the gate electrode and on the source/drain regions, removing the silicon nitride sidewall spacers, pre-amorphizing the intended source/drain extension regions, ion implanting impurities into the pre-amorphized regions and laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions.

摘要翻译： 包括具有精确定义的单晶或基本上完全单晶硅源极/漏极延伸的完全和部分耗尽的SOI晶体管的半导体器件通过将预期的源/漏延伸，离子注入掺杂剂预先非晶化以进行预非晶化区域和激光热退火来制造 源/漏扩展的结晶和激活。 实施例包括在SOI衬底之上形成栅极电介质层，在栅电极之间形成氮化硅侧壁间隔物，形成源/漏区，在栅电极和源极上形成热氧化层 漏极区域，去除氮化硅侧壁间隔物，使预期的源极/漏极延伸区域预非晶化，离子注入杂质到预非晶化区域和激光热退火以使预非晶化区域结晶并激活源极/漏极延伸部分 。

公开(公告)号：US06696348B1

公开(公告)日：2004-02-24

申请号：US10314326

申请日：2002-12-09

申请人： Qi Xiang

发明人： Qi Xiang

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： The present invention enables the production of improved high-speed semiconductor devices. The present invention provides the higher speed offered by strained silicon technology coupled with the smaller overall device size provided by shallow trench isolation technology without relaxation of the portion of the strained silicon layer adjacent to a shallow trench isolation region by laterally extending a shallow trench isolation into the strained silicon layer overlying a silicon germanium layer.

摘要翻译： 本发明能够制造改进的高速半导体器件。 本发明提供了由应变硅技术提供的更高速度，以及由浅沟槽隔离技术提供的较小的整体器件尺寸，而不会通过将浅沟槽隔离横向延伸到浅沟槽隔离部分而使弛豫与浅沟槽隔离区域相邻的应变硅层的部分松弛 覆盖硅锗层的应变硅层。

公开(公告)号：US06660578B1

公开(公告)日：2003-12-09

申请号：US10118274

申请日：2002-04-08

申请人： Olov Karlsson ,  Qi Xiang ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic

发明人： Olov Karlsson ,  Qi Xiang ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic

IPC分类号： H01L218238

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A semiconductor device, a semiconductor wafer and a method of forming a semiconductor wafer where a barrier layer is used to inhibit P-type ion-penetration into a dielectric layer made from a high-K material.

摘要翻译： 半导体器件，半导体晶片和形成半导体晶片的方法，其中阻挡层用于抑制由高K材料制成的电介质层中的P型离子渗透。

公开(公告)号：US06630720B1

公开(公告)日：2003-10-07

申请号：US10036210

申请日：2001-12-26

申请人： Witold P. Maszara ,  HaiHong Wang ,  Qi Xiang

发明人： Witold P. Maszara ,  HaiHong Wang ,  Qi Xiang

IPC分类号： H01L2976

CPC分类号： H01L21/823842 ,  H01L21/0337 ,  H01L21/84 ,  H01L27/1203

摘要： An asymmetric semiconductor device and a method of making a pair of the asymmetric devices. The semiconductor device includes a layer of semiconductor material having a source and a drain, and a dual work function gate disposed on the layer of semiconductor material to define a channel interposed between the source and the drain.

摘要翻译： 非对称半导体器件和制造一对不对称器件的方法。 半导体器件包括具有源极和漏极的半导体材料层，以及设置在半导体材料层上以限定插入在源极和漏极之间的沟道的双功函数栅极。

公开(公告)号：US06602781B1

公开(公告)日：2003-08-05

申请号：US09734207

申请日：2000-12-12

申请人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

发明人： Qi Xiang ,  Paul R. Besser ,  Matthew Buynoski ,  John C. Foster ,  Paul L. King ,  Eric N. Paton

IPC分类号： H01L2144

CPC分类号： H01L21/28202 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833

摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining a metal within a recess overlying a channel and annealing to cause metal and its overlying silicon to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The metal is removed except for the portion of the metal in the recess. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.

摘要翻译： 实现自对准金属硅化物栅极的方法是通过将金属限制在覆盖沟道的凹槽内并退火以使金属及其上覆的硅相互作用以形成自对准的金属硅化物栅极来实现的。 在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。 除了金属在凹部中的部分之外，除去金属。 进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

公开(公告)号：US06524929B1

公开(公告)日：2003-02-25

申请号：US09794894

申请日：2001-02-26

申请人： Qi Xiang ,  Philip A. Fisher

发明人： Qi Xiang ,  Philip A. Fisher

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283

摘要： A method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric insulation layer and a silicon substrate; forming an isolation trench through the silicon active layer, the isolation trench defining at least one active island in the silicon active layer; depositing a passivating insulator in a lower portion of the isolation trench; and filling the isolation trench above the passivating insulator with a trench isolation material.

摘要翻译： 一种隔离绝缘体上半导体器件上的有源岛的方法，包括以下步骤：提供具有硅有源层，介电绝缘层和硅衬底的绝缘体上硅半导体晶片; 通过所述硅有源层形成隔离沟槽，所述隔离沟槽限定所述硅有源层中的至少一个有源岛; 在隔离沟槽的下部沉积钝化绝缘体; 以及用沟槽隔离材料填充钝化绝缘体上方的隔离沟槽。