Abstract:
A method and apparatus for processing a bevel edge is provided. A substrate is placed in a bevel processing chamber and a passivation layer is formed on the substrate only around a bevel region of the substrate using a passivation plasma confined in a peripheral region of the bevel processing chamber. The substrate may undergo a subsequent semiconductor process, during which the bevel edge region of the substrate is protected by the passivation layer. Alternatively, the passivation layer may be patterned using a patterning plasma formed in an outer peripheral region of the processing chamber, the patterning plasma being confined by increasing plasma confinement. The passivation layer on outer edge portion of the bevel region is removed, while the passivation layer on an inner portion of the bevel region is maintained. The bevel edge of the substrate may be cleaned using the patterned passivation layer as a protective mask.
Abstract:
A method for etching a bevel edge of a substrate is provided. A patterned photoresist mask is formed over the etch layer. The bevel edge is cleaned comprising providing a cleaning gas comprising at least one of a CO2, CO, CxHy, H2, NH3, CxHyFz and a combination thereof, forming a cleaning plasma from the cleaning gas, and exposing the bevel edge to the cleaning plasma. Features are etched into the etch layer through the photoresist features and the photoresist mask is removed.
Abstract translation:提供了蚀刻基板的斜边缘的方法。 在蚀刻层上形成图案化的光致抗蚀剂掩模。 清洁斜面边缘,包括提供包括CO 2,CO,C x H y,H 2,NH 3,C x H y Fz及其组合中的至少一种的清洁气体,从清洁气体形成清洁等离子体,并将斜面边缘暴露于清洁等离子体 。 通过光致抗蚀剂特征将特征蚀刻到蚀刻层中,并去除光致抗蚀剂掩模。
Abstract:
Systems and methods, including computer software implementations, involve identifying a first set of device capabilities associated with an electronic device. The first set of device capabilities include one or more device capabilities. A description of the first set of device capabilities is provided to a remote source, and a first device profile identifier is received from the remote source. The first device profile identifier is associated with the first set of device capabilities. The first device profile identifier is stored on the electronic device, and the received first device profile identifier is included in a communication to the remote source.
Abstract:
A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.
Abstract:
To key an identification code of a controlling member to a code reader of a function controller for controlling a function, each controlling member is fitted with a card reader and is configured to adopt the code on the card as the identification code to be attached as the identification portion of any message imparted into a signal line. In similar fashion, each of the function controllers includes a card reader for reading a card bearing a code and the function controller is configured to adopt the code read from the card as being the identification code sought by the function controller as identifying a message as originating from its associated controlling member.
Abstract:
Systems and methods, including computer software implementations, involve identifying a first set of device capabilities associated with an electronic device. The first set of device capabilities include one or more device capabilities. A description of the first set of device capabilities is provided to a remote source, and a first device profile identifier is received from the remote source. The first device profile identifier is associated with the first set of device capabilities. The first device profile identifier is stored on the electronic device, and the received first device profile identifier is included in a communication to the remote source.
Abstract:
A battery core is made from a strip of insulating material folded longitudinally to form parallel panels. In one embodiment there are four panels and in another five panels. A positive electrode strip has an exposed foil center strip and positive electrode material along both edges. The positive electrode is folded around one fold of the insulator with the strip of foil exposed at the fold. A negative electrode strip has an exposed center strip and negative electrode material along both edges. The negative electrode is folded around a different fold of the insulator with the strip of foil exposed.
Abstract:
A wafer level vertical diode package structure includes a first semiconductor layer, a second semiconductor layer, an insulative unit, a first conductive structure, and a second conductive structure. The second semiconductor layer is connected with one surface of the first semiconductor layer. The insulative unit is disposed around a lateral side of the first semiconductor layer and a lateral side of the second semiconductor layer. The first conductive structure is formed on a top surface of the first semiconductor layer and on one lateral side of the insulative layer. The second conductive structure is formed on a top surface of the second semiconductor layer and on another opposite lateral side of the insulative layer.
Abstract:
This invention provides thermal sensors and imagers that are flexible and capable of conforming to curved surfaces and corresponding methods of making and methods of thermal sensing. The thermal sensors contain an array of thermal resistors patterned in a row and column configuration, with each thermal resistor electrically isolated from other thermal resistors within the sensor. Thermal information is obtained from a region by measuring the resistance of each thermal resistor and calculating a thermal resistance for each entry of the array.
Abstract:
A wafer level vertical diode package structure includes a first semiconductor layer, a second semiconductor layer, an insulative unit, a first conductive structure, and a second conductive structure. The second semiconductor layer is connected with one surface of the first semiconductor layer. The insulative unit is disposed around a lateral side of the first semiconductor layer and a lateral side of the second semiconductor layer. The first conductive structure is formed on a top surface of the first semiconductor layer and on one lateral side of the insulative layer. The second conductive structure is formed on a top surface of the second semiconductor layer and on another opposite lateral side of the insulative layer.