公开(公告)号：US5200352A

公开(公告)日：1993-04-06

申请号：US797580

申请日：1991-11-25

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L21/225 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/66628 ,  H01L21/2257 ,  H01L21/823814 ,  H01L29/66287 ,  H01L29/66492 ,  H01L29/6653 ,  Y10S257/90

摘要： A transistor (10 or 11) and method of formation. The transistor (10) has a substrate (12). The substrate (12) has an overlying dielectric layer (14) and an insulated conductive control electrode (16) which overlies the dielectric layer (14). A dielectric region (18) overlies the insulated conductive control electrode (16), and a dielectric region (20) is adjacent to the insulated conductive control electrode (16). A spacer (30) is adjacent to the dielectric region (20). Epitaxial regions (24) are adjacent to the spacer (30) and the spacer (30) is overlying portions of the epitaxial regions (24). A dielectric region (26) overlies the epitaxial regions (24). Highly doped source and drain regions (32) underlie the epitaxial regions (24). LDD regions (28), which are underlying the spacer (30), are adjacent to and electrically connected to the source and drain regions (32).

摘要翻译： 一种晶体管（10或11）及其形成方法。 晶体管（10）具有基板（12）。 衬底（12）具有覆盖在电介质层（14）上的上覆电介质层（14）和绝缘导电控制电极（16）。 电介质区域（18）覆盖绝缘导电控制电极（16），电介质区域（20）与绝缘导电控制电极（16）相邻。 间隔物（30）与电介质区域（20）相邻。 外延区域（24）与间隔物（30）相邻，并且间隔物（30）覆盖外延区域（24）的部分。 电介质区域（26）覆盖在外延区域（24）上。 高掺杂源极和漏极区域（32）位于外延区域（24）的下面。 位于间隔物（30）下方的LDD区域（28）与源区和漏区（32）相邻并电连接。

公开(公告)号：US4966864A

公开(公告)日：1990-10-30

申请号：US329167

申请日：1989-03-27

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L21/768

CPC分类号： H01L21/76838

摘要： A semiconductor device structure including a contact and a method for its fabrication are disclosed. In accordance with one embodiment of the disclosure, a contact is formed between a monocrystalline silicon substrate and an overlying silicon layer. A silicon substrate is provided which has a first insulating layer formed thereon. A layer of silicon is deposited and patterned over the insulator layer. The patterned silicon layer is then oxidized and a contact opening is etched through the first insulator layer and the silicon dioxide is expose portions of the silicon substrate and an adjacent portion of the patterned silicon layer. A further layer of polycrystalline silicon is then selectively deposited onto the exposed portions of the substrate and silicon layer to form an electrical connection between the two.

摘要翻译： 公开了一种包括接触的半导体器件结构及其制造方法。 根据本公开的一个实施例，在单晶硅衬底和上覆硅层之间形成接触。 提供了在其上形成有第一绝缘层的硅衬底。 在绝缘体层上沉积并图案化硅层。 图案化硅层然后被氧化，并且通过第一绝缘体层蚀刻接触开口，并且二氧化硅暴露硅衬底的部分和图案化硅层的相邻部分。 然后将另一层多晶硅选择性地沉积到衬底和硅层的暴露部分上以在两者之间形成电连接。

公开(公告)号：US4928156A

公开(公告)日：1990-05-22

申请号：US319000

申请日：1989-03-06

申请人： John R. Alvis ,  James R. Pfiester ,  Orin W. Holland

发明人： John R. Alvis ,  James R. Pfiester ,  Orin W. Holland

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/08 ,  H01L29/167 ,  H01L29/36 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/36 ,  H01L29/7836 ,  Y10S257/919

摘要： Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n.sup.- and n.sup.+ regions in GSDs and LDDs.

摘要翻译： 具有n型源极/漏极区域的金属氧化物半导体（MOS）晶体管在源/漏极中或附近也具有锗掺杂区域。 分级源极漏极（GSD），轻掺杂漏极（LDD）和双扩散漏极（DDD）中磷附近或位置处的锗的存在提供了漏极区的更好的轮廓，其结点深度低于磷获得的结点深度 或特别是磷和砷一起。 获得漏极结的良好分级，以避免热载流子不稳定或热载流子注入问题，同时连接浅源极结，这可以最大限度地减小横向掺杂剂扩散，并减小GSD和LDD中n +和n +区之间的距离。

公开(公告)号：US4786611A

公开(公告)日：1988-11-22

申请号：US109636

申请日：1987-10-19

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L21/3215 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/225

CPC分类号： H01L21/823835 ,  H01L21/32155 ,  H01L21/823842 ,  H01L27/0928 ,  Y10S148/147

摘要： Adjusting field effect transistor (FET) threshold voltage (V.sub.T) by diffusing impurities in polysilicon gates through a refractory metal silicide. Dopants of different conductivities may be cross-diffused. This adjustment can be made relatively late in the fabrication of the wafers to provide a quick turn around time of custom circuits, gate arrays and application specific integrated circuits (ASICs). A masking step selectively provides blocking elements to prevent the diffusion from occurring in certain of the FETs.

摘要翻译： 通过在难熔金属硅化物中扩散多晶硅栅极中的杂质来调节场效应晶体管（FET）阈值电压（VT）。 不同电导率的掺杂剂可能是交叉扩散的。 这种调整可以在制造晶片时相对较晚，以提供定制电路，门阵列和专用集成电路（ASIC）的快速转动时间。 掩蔽步骤选择性地提供阻挡元件以防止在某些FET中发生扩散。

公开(公告)号：US4745079A

公开(公告)日：1988-05-17

申请号：US31299

申请日：1987-03-30

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/336 ,  H01L29/49 ,  H01L21/265

CPC分类号： H01L29/66575 ,  H01L21/28105 ,  H01L21/32155 ,  H01L29/4983 ,  Y10S148/082

摘要： A method for fabricating an insulated gate field effect transistor (IGFET) having a semiconductor gate with a first portion and a second portion where the portions are of two different conductivity types. Typically, a central portion of the gate, such as a doped polysilicon gate of a first conductivity type, is flanked by end portions near the source/drain regions, where the end portions are doped with an impurity of a second conductivity type. A semiconductor material layer, such as polycrystalline silicon (polysilicon) is selectively protected by a gate pattern mask whereby the end portions of the gates are produced by the lateral diffusion of the dopant under the edges of the gate pattern mask. Thus, the technique for defining the different portions of the gate uses other than photolithographic techniques which are limited in their resolution capabilities, and thus is readily implementable in submicron device feature processes.

摘要翻译： 一种用于制造具有半导体栅极的绝缘栅场效应晶体管（IGFET）的方法，所述半导体栅极具有第一部分和第二部分，其中所述部分具有两种不同的导电类型。 通常，栅极的中心部分，例如第一导电类型的掺杂多晶硅栅极，其侧面是靠近源极/漏极区域的端部，其中末端部分掺杂有第二导电类型的杂质。 诸如多晶硅（多晶硅）的半导体材料层被栅极图案掩模选择性地保护，由此通过栅极图案掩模的边缘处的掺杂剂的横向扩散来产生栅极的端部。 因此，用于限定栅极的不同部分的技术使用除了其分辨能力受限的光刻技术之外，因此可以在亚微米器件特征过程中容易地实现。

公开(公告)号：US5473185A

公开(公告)日：1995-12-05

申请号：US341259

申请日：1994-11-17

申请人： James R. Pfiester ,  James D. Hayden

发明人： James R. Pfiester ,  James D. Hayden

IPC分类号： H01L27/11 ,  H01L21/8244 ,  H01L29/78

CPC分类号： H01L27/11 ,  Y10S257/903

摘要： An SRAM cell is formed such that pass channel-stop regions, which are adjacent to the pass transistors, have a higher doping concentration compared to the latch channel-stop regions that are adjacent to the latch transistors. In one embodiment, the pass channel-stop regions are formed using two channel-stop doping steps, whereas the latch channel-stop regions are formed during only one channel-stop doping step. The doping steps may be performed before or after field isolation is formed. The higher doping concentration causes the dopant from the pass channel-stop regions to extend laterally further from the edge of the field isolation compared to the latch channel-stop regions. The process can be adapted for use in almost any type of field isolation process.

摘要翻译： 形成SRAM单元，使得与与锁存晶体管相邻的锁存通道停止区域相比，与通过晶体管相邻的通过通道停止区域具有较高的掺杂浓度。 在一个实施例中，通道通道停止区域是使用两个通道停止掺杂步骤形成的，而锁存通道停止区域仅在一个通道停止掺杂步骤期间形成。 掺杂步骤可以在形成场隔离之前或之后进行。 与锁存通道停止区域相比，较高的掺杂浓度使来自通道 - 停止区域的掺杂剂从场隔离的边缘横向延伸。 该过程可以适用于几乎任何类型的现场隔离过程。

公开(公告)号：US5422300A

公开(公告)日：1995-06-06

申请号：US291781

申请日：1994-08-17

申请人： James R. Pfiester ,  Prashant Kenkare ,  Kent J. Cooper ,  Bich-Yen Nguyen

发明人： James R. Pfiester ,  Prashant Kenkare ,  Kent J. Cooper ,  Bich-Yen Nguyen

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762

CPC分类号： H01L21/32 ,  H01L21/76202

摘要： Defect-free field oxide isolation is achieved using a laminated layer (14) of thermal silicon dioxide and chemically vapor deposited silicon dioxide underneath a silicon nitride field oxidation mask (18). The laminated layer (14) of silicon dioxide is formed on a silicon substrate (12) and a layer of silicon nitride is then deposited over it. The silicon nitride is subsequently patterned to form a field oxidation mask (18) which defines isolation regions (22) within the silicon substrate (12). Field oxide (34) is grown in the isolation regions (22) of the silicon substrate (12) and the field oxidation mask (18) is subsequently removed.

摘要翻译： 使用热二氧化硅的层叠层（14）和在氮化硅场氧化掩模（18）下方的化学气相沉积二氧化硅来实现无缺陷的场氧化物隔离。 二氧化硅层叠层（14）形成在硅衬底（12）上，然后在其上沉积氮化硅层。 氮化硅随后被图案化以形成限定硅衬底（12）内的隔离区域（22）的场氧化掩模（18）。 场氧化物（34）生长在硅衬底（12）的隔离区（22）中，随后去除场氧化掩模（18）。

公开(公告)号：US5405806A

公开(公告)日：1995-04-11

申请号：US219328

申请日：1994-03-29

申请人： James R. Pfiester ,  James D. Hayden ,  Michael P. Woo

发明人： James R. Pfiester ,  James D. Hayden ,  Michael P. Woo

IPC分类号： H01L21/768 ,  H01L21/283 ,  H01L21/336

CPC分类号： H01L21/76895 ,  H01L21/76889 ,  Y10S148/019 ,  Y10S148/147

摘要： A metal silicide interconnect (48, 92, 124) is formed in an integrated circuit using a sacrificial layer (30, 78, 108). In one embodiment a sacrificial layer of titanium nitride (30) is formed overlying a semiconductor substrate (12) and a polysilicon conductive member (20). The sacrificial titanium nitride layer (30) is then patterned and an underlying portion (40) of the semiconductor substrate (12), and a sidewall portion (42) of the polysilicon conductive member (20) are subsequently exposed. A metal layer (46) is deposited and then reacted with the exposed portion 40 of the semiconductor substrate (12) and the exposed sidewall (42) of the polysilicon conductive member (20) to form a metal silicide interconnect (48). The remaining portion of the sacrificial titanium nitride layer (38) is then removed after the metal silicide interconnect (48) has been formed without substantially altering the metal silicide interconnect (48).

摘要翻译： 金属硅化物互连（48,92,124）在使用牺牲层（30,78,108）的集成电路中形成。 在一个实施例中，氮化钛（30）的牺牲层形成在半导体衬底（12）和多晶硅导电部件（20）之上。 然后对牺牲氮化钛层（30）进行图案化，随后露出半导体衬底（12）的下部（40）和多晶硅导电部件（20）的侧壁部分（42）。 沉积金属层（46），然后与半导体衬底（12）的暴露部分40和多晶硅导电构件（20）的暴露的侧壁（42）反应以形成金属硅化物互连（48）。 然后在形成金属硅化物互连（48）之后，基本上不改变金属硅化物互连（48），去除牺牲氮化钛层（38）的剩余部分。

公开(公告)号：US5373170A

公开(公告)日：1994-12-13

申请号：US31513

申请日：1993-03-15

申请人： James R. Pfiester ,  James D. Hayden

发明人： James R. Pfiester ,  James D. Hayden

IPC分类号： H01L27/11 ,  H01L27/01

CPC分类号： H01L27/1108 ,  Y10S257/903

摘要： A semiconductor memory cell (10) having a symmetrical layout is fabricated in first and second active regions (44, 46) of a semiconductor substrate (11). A first driver transistor (16) resides in the second active region (46), and a second driver transistor (20) resides in the first active region (44). The second driver transistor (20) has a gate electrode (55) overlying a portion of the first active region (44) and is electrically coupled to the second active region (46). A thin-film load transistor (18) resides over the first active region (44), the thin-film load transistor (18) has a thin-film channel layer (23) that overlies, and is aligned with, the gate electrode (55) of the second driver transistor (20). A second portion of the thin-film channel layer (23) extends away from the first active region (44) to form a Vcc node (36). A Vcc interconnect layer (82) overlies the thin-film load transistors and the driver transistors. The Vcc interconnect layer (82) is electrically isolated from the thin-film gate electrode and electrically contacts the second portion of the thin-film channel layer (23) at Vcc node (36). A thin-film load transistor (22) having structure corresponding with thin-film load transistor (20) resides over the second active region (46).

摘要翻译： 在半导体衬底（11）的第一和第二有源区（44,46）中制造具有对称布局的半导体存储单元（10）。 第一驱动晶体管（16）位于第二有源区（46）中，第二驱动晶体管（20）位于第一有源区（44）中。 第二驱动晶体管（20）具有覆盖第一有源区（44）的一部分并且电耦合到第二有源区（46）的栅电极（55）。 薄膜负载晶体管（18）位于第一有源区（44）之上，薄膜负载晶体管（18）具有薄膜沟道层（23），该薄膜沟道层覆盖并与栅电极 55）的第二驱动晶体管（20）。 薄膜通道层（23）的第二部分远离第一有源区（44）延伸以形成Vcc节点（36）。 Vcc互连层（82）覆盖薄膜负载晶体管和驱动晶体管。 Vcc互连层（82）与薄膜栅电极电隔离，并在Vcc节点（36）处与薄膜沟道层（23）的第二部分电接触。 具有与薄膜负载晶体管（20）对应的结构的薄膜负载晶体管（22）位于第二有源区（46）上。

公开(公告)号：US5371035A

公开(公告)日：1994-12-06

申请号：US11621

申请日：1993-02-01

申请人： James R. Pfiester ,  Philip J. Tobin

发明人： James R. Pfiester ,  Philip J. Tobin

IPC分类号： H01L21/306 ,  H01L21/32 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/32 ,  H01L21/30604 ,  H01L21/76202

摘要： A layer of silicon-germanium (57) allows electrical isolation structures, having reduced field oxide encroachment, to be formed without adversely effecting the adjacent active regions (64). A high etch selectivity between silicon-germanium and the silicon substrate (52) allows the silicon-germanium layer (57) to be removed, after field oxidation, without damaging the underlying active regions (64).

摘要翻译： 一层硅 - 锗（57）允许形成具有减小的场氧化物侵蚀的电隔离结构，而不会不利地影响相邻的有源区（64）。 硅 - 锗和硅衬底（52）之间的高蚀刻选择性允许在场氧化之后去除硅 - 锗层（57），而不会损坏下面的有源区域（64）。