利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

38 条记录 (耗时 0.041 秒)

    Self-aligned implanted waveguide detector
    31.
    发明申请
    Self-aligned implanted waveguide detector 失效
    自对准植入波导检测器

    公开(公告)号：US20050212068A1

    公开(公告)日：2005-09-29

    申请号：US10959897

    申请日：2004-10-06

    申请人： Francisco Leon ,  Lawrence West

    发明人： Francisco Leon ,  Lawrence West

    IPC分类号： H01L27/14

    CPC分类号： H01L31/035254 ,  B82Y20/00 ,  G02B6/12004

    摘要： A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the first sidewall to form a first conductive region that has a top end that is part of the top end of the island; implanting a second dopant into the second sidewall to form a second conductive region that has a top end that is part of the top end of the island; fabricating a first electrical connection to the top end of the first conductive region; and fabricating a second electrical connection to the top end of the second conductive region.

    摘要翻译： 一种制造检测器的方法，所述方法包括在衬底上形成检测器芯材料岛，所述岛具有水平取向的顶端，垂直取向的第一侧壁和与所述第一侧壁相对的垂直取向的第二侧壁; 将第一掺杂剂注入到所述第一侧壁中以形成具有作为所述岛的顶端的一部分的顶端的第一导电区域; 将第二掺杂剂注入所述第二侧壁中以形成具有作为所述岛的顶端的一部分的顶端的第二导电区域; 制造到第一导电区域的顶端的第一电连接; 以及制造到所述第二导电区域的顶端的第二电连接。

    Solution to thermal budget
    32.
    发明申请
    Solution to thermal budget 失效
    热预算解决方案

    公开(公告)号：US20050054131A1

    公开(公告)日：2005-03-10

    申请号：US10896754

    申请日：2004-07-22

    申请人： Yuichi Wada ,  Francisco Leon

    发明人： Yuichi Wada ,  Francisco Leon

    IPC分类号： C30B29/12 ,  C30B33/00 ,  G02B6/12 ,  G02B6/42 ,  G02B6/43 ,  H01L21/00 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/84 ,  H01L27/12 ,  H01L31/0352

    CPC分类号： G02B6/12004 ,  B82Y20/00 ,  C30B29/12 ,  C30B33/00 ,  G02B6/12 ,  G02B6/4214 ,  G02B6/43 ,  H01L21/84 ,  H01L27/1203 ,  H01L31/035254

    摘要： A method of fabricating on optical detector, the method including providing a substrate that includes an optical waveguide formed therein and having a surface for fabricating microelectronic circuitry thereon; fabricating microelectronic circuitry on the substrate, the fabricating involving a plurality of sequential process phases; after a selected one of the plurality of sequential process phases has occurred and before the next process phase after the selected one of the plurality of process phases begins, fabricating an optical detector within the optical waveguide; and after fabricating the optical detector in the waveguide, completing the plurality of sequential process phases for fabricating the microelectronic circuitry.

    摘要翻译： 一种在光学检测器上制造的方法，所述方法包括提供包括其中形成的光波导并且具有用于在其上制造微电子电路的表面的衬底; 在衬底上制造微电子电路，该制造涉及多个连续的工艺阶段; 在所述多个顺序处理阶段中的所选择的一个已经发生并且在所述多个处理阶段中所选择的一个处理阶段开始之后的下一个处理阶段之前，在所述光波导内制造光学检测器; 并且在波导中制造光学检测器之后，完成用于制造微电子电路的多个顺序处理阶段。

    Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires
    36.
    发明申请
    Fully integrated organic layered processes for making plastic electronics based on conductive polymers and semiconductor nanowires 失效
    用于制造基于导电聚合物和半导体纳米线的塑料电子器件的完全集成的有机分层工艺

    公开(公告)号：US20060214156A1

    公开(公告)日：2006-09-28

    申请号：US11233503

    申请日：2005-09-22

    申请人： Yaoling Pan ,  Francisco Leon ,  David Stumbo

    发明人： Yaoling Pan ,  Francisco Leon ,  David Stumbo

    IPC分类号： H01L29/08

    CPC分类号： H01L51/0545 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0541 ,  H01L51/0566 ,  H01L51/4253 ,  H01L51/4266 ,  Y02E10/549 ,  Y02P70/521 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/764

    摘要： The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.

    摘要翻译： 本发明涉及使用并入和/或设置在导电聚合物层附近的纳米线（或诸如纳米带，纳米管等的其它纳米结构）的薄膜晶体管，以及用于生产这种晶体管的生产可扩展方法。 特别地，公开了包含导电聚合材料如聚苯胺（PANI）或聚吡咯（PPY）和一个或多个纳米线的复合材料，其中并入其中。 还提供了几种纳米线TFT制造方法，其在一个示例性实施例中包括提供器件衬底; 在器件衬底上沉积第一导电聚合物材料层; 限定所述导电聚合物层中的一个或多个栅极接触区域; 在所述导电聚合物层上以足够的纳米线密度沉积多个纳米线以实现工作电流水平; 在所述多个纳米线上沉积第二导电聚合物材料层; 以及在所述第二导电聚合物材料层中形成源极和漏极接触区域，从而提供与所述多个纳米线的电连接性，由此所述纳米线形成在所述源极和漏极区域中的相应长度之间具有长度的沟道。

    Embedded waveguide detectors
    38.
    发明申请
    Embedded waveguide detectors 失效
    嵌入式波导检测器

    公开(公告)号：US20050051767A1

    公开(公告)日：2005-03-10

    申请号：US10856750

    申请日：2004-05-28

    申请人： Francisco Leon ,  Lawrence West ,  Yuichi Wada ,  Gregory Wojcik ,  Stephen Moffatt

    发明人： Francisco Leon ,  Lawrence West ,  Yuichi Wada ,  Gregory Wojcik ,  Stephen Moffatt

    IPC分类号： G02B20060101 ,  G02B6/12 ,  H01L29/06 ,  H01L31/0232

    CPC分类号： G02B6/12004 ,  G02B2006/12061 ,  H01L31/0232 ,  H01L31/0288 ,  H01L31/105 ,  H01L31/1812 ,  Y02E10/50

    摘要： A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.

    摘要翻译： 一种制造检测器的方法，包括：在衬底中形成沟槽，所述衬底具有上表面; 在所述衬底和所述沟槽中形成第一掺杂半导体层; 在所述第一掺杂半导体层上形成第二半导体层并延伸到所述沟槽中，所述第二半导体层的导电率小于所述第一掺杂半导体层的导电性; 在所述第二半导体层上形成第三掺杂半导体层并延伸到所述沟槽中; 去除在由衬底的表面限定的平面之上的第一层，第二层和第三层的部分，以产生上部基本平坦的表面，并且暴露沟槽中的第一掺杂半导体层的上端; 形成第一电接触到第一半导体掺杂层; 以及向所述第三半导体掺杂层形成第二电接触。