公开(公告)号：US07915653B2

公开(公告)日：2011-03-29

申请号：US11556755

申请日：2006-11-06

申请人： Jack O. Chu ,  Gabriel K. Dehlinger ,  Alfred Grill ,  Steven J. Koester ,  Qiqing Ouyang ,  Jeremy D. Schaub

发明人： Jack O. Chu ,  Gabriel K. Dehlinger ,  Alfred Grill ,  Steven J. Koester ,  Qiqing Ouyang ,  Jeremy D. Schaub

IPC分类号： H01L27/146

CPC分类号： H01L31/101

摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

摘要翻译： 本发明解决了与Si CMOS技术兼容的高速高效光电探测器的问题。 该结构由薄的SOI衬底上的Ge吸收层组成，并且使用隔离区，交替的n型和p型接触以及低电阻表面电极。 该器件通过利用掩埋绝缘层，通过利用Ge吸收层，利用薄吸收层和窄电极间隔的低电压操作以及兼容性来兼容通过利用掩埋绝缘层来隔离在下面的衬底中产生的载流子，在广谱上的高量子效率， 通过其平面结构和使用IV族吸收材料的CMOS器件。 用于制造光电检测器的方法使用在薄SOI或外延氧化物上的Ge的直接生长，以及随后的热退火以实现高质量的吸收层。 该方法限制可用于相互扩散的Si的量，从而允许Ge层退火，而不会导致Ge层被下面的Si大量稀释。

公开(公告)号：US07678634B2

公开(公告)日：2010-03-16

申请号：US12020916

申请日：2008-01-28

申请人： Qiqing Ouyang ,  Kathryn T. Schonenberg

发明人： Qiqing Ouyang ,  Kathryn T. Schonenberg

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： A first dielectric layer is formed over a PFET gate and an NFET gate, and lithographically patterned to expose a PFET area, while covering an NFET area. Exposed PFET active area is etched and refilled with a SiGe alloy, which applies a uniaxial compressive stress to a PFET channel. A second dielectric layer is formed over the PFET gate and the NFET gate, and lithographically patterned to expose the NFET area, while covering the PFET area. Exposed NFET active area is etched and refilled with a silicon-carbon alloy, which applies a uniaxial tensile stress to an NFET channel. Dopants may be introduced into the SiGe and silicon-carbon regions by in-situ doping or by ion implantation.

摘要翻译： 在PFET栅极和NFET栅极上形成第一电介质层，并且被光刻图案化以在覆盖NFET区域的同时暴露PFET区域。 暴露的PFET有源区被蚀刻并用SiGe合金重新填充，SiGe合金向PFET通道施加单轴压应力。 第二电介质层形成在PFET栅极和NFET栅极上，并且被光刻图案化以暴露NFET区域，同时覆盖PFET区域。 暴露的NFET有源区被蚀刻并用硅 - 碳合金重新填充，硅 - 碳合金对NFET通道施加单轴拉伸应力。 可以通过原位掺杂或通过离子注入将掺杂剂引入到SiGe和硅 - 碳区域中。

公开(公告)号：US20090298297A1

公开(公告)日：2009-12-03

申请号：US12538110

申请日：2009-08-08

申请人： Thomas S. Kanarsky ,  Qiqing Ouyang ,  Haizhou Yin

发明人： Thomas S. Kanarsky ,  Qiqing Ouyang ,  Haizhou Yin

IPC分类号： H01L21/31

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/7843 ,  H01L29/7847

摘要： A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.

摘要翻译： 在至少一个PFET和至少一个NFET上形成应力传导电介质层。 通过毯式沉积和图案化在至少一个NFET上形成拉伸应力产生膜，例如氮化硅。 可以通过覆盖沉积和图案化在至少一个PFET上形成可以是折射金属氮化物膜的压应力产生膜。 在压缩应力产生膜上沉积密封电介质膜。 应力从拉伸应力产生膜和压缩应力产生膜转移到下面的半导体结构中。 来自难熔金属氮化物膜的转移的压缩应力的大小可以为约5GPa至约20GPa。 应力在退火期间被记忆，并且在除去应力产生膜之后保留在半导体器件中。

公开(公告)号：US20080132025A1

公开(公告)日：2008-06-05

申请号：US11877305

申请日：2007-10-23

申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

IPC分类号： H01L21/331

CPC分类号： H01L29/7317

摘要： The present invention provides a “collector-less” silcon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BIJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

摘要翻译： 本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SIL）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。 根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反转层。这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BIJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

公开(公告)号：US20080083955A1

公开(公告)日：2008-04-10

申请号：US11538506

申请日：2006-10-04

申请人： Thomas S. Kanarsky ,  Qiqing Ouyang ,  Kathryn T. Schonenberg ,  Chun-Yung Sung

发明人： Thomas S. Kanarsky ,  Qiqing Ouyang ,  Kathryn T. Schonenberg ,  Chun-Yung Sung

IPC分类号： H01L29/76

CPC分类号： H01L29/7833 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76841 ,  H01L21/76865 ,  H01L29/7843 ,  H01L29/7845

摘要： A stressed liner for improving carrier mobility in a transistor and a method for fabricating the same is disclosed. The stressed liner includes an intrinsically stressed conductive film encapsulated between two insulating layers such as silicon nitride, silicon oxide, or oxynitride. The stressed liner may be compressively-stressed or tensile-stressed depending on whether an n-FET or p-FET is required.

摘要翻译： 公开了一种用于改善晶体管中的载流子迁移率的应力衬垫及其制造方法。 应力衬里包括密封在两个绝缘层（例如氮化硅，氧化硅或氮氧化物）之间的本征应力导电膜。 根据是否需要n-FET或p-FET，应力衬垫可以是压应力或拉伸应力。

公开(公告)号：US20070111417A1

公开(公告)日：2007-05-17

申请号：US11619511

申请日：2007-01-03

申请人： Andres Bryant ,  Qiqing Ouyang ,  Kern Rim

发明人： Andres Bryant ,  Qiqing Ouyang ,  Kern Rim

IPC分类号： H01L21/8234 ,  H01L29/76 ,  H01L21/336 ,  H01L29/94

CPC分类号： H01L21/823807 ,  H01L21/7624 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7849

摘要： The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.

摘要翻译： 本发明提供半导体器件及其形成方法，其中在半导体器件的器件沟道中产生单轴应变。 单轴应变可以处于张力或压缩状态，并且在平行于装置通道的方向上。 单轴应变可以通过应变诱导衬片，应变诱导孔或其组合在双轴应变衬底表面中产生。 单轴应变可以通过应变诱导孔和应变诱导衬垫的组合在松弛的衬底中产生。 本发明还提供了用应变诱导隔离区增加双轴应变的方法。 本发明还提供了CMOS器件，其中可以独立地处理CMOS衬底的器件区域以提供压缩或张力的单轴应变半导体表面。

公开(公告)号：US20070108536A1

公开(公告)日：2007-05-17

申请号：US11164215

申请日：2005-11-15

申请人： MeiKei Ieong ,  Thomas Ludwig ,  Edward Nowak ,  Qiqing Ouyang

发明人： MeiKei Ieong ,  Thomas Ludwig ,  Edward Nowak ,  Qiqing Ouyang

IPC分类号： H01L21/8244

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66818 ,  H01L29/785

摘要： A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material. The present invention also relates to the resultant semiconductor structure that is formed utilizing the method of the present invention.

摘要翻译： 提供了一种形成包括多个finFFET器件的半导体结构的方法，其中使用交叉掩模提供矩形图案以限定相对薄的金属丝以及化学氧化物去除（COR）工艺。 本方法还包括通过使用选择性含硅材料来合并相邻的金属丝的步骤。 本发明还涉及利用本发明的方法形成的所得半导体结构。

公开(公告)号：US20070051996A1

公开(公告)日：2007-03-08

申请号：US11553072

申请日：2006-10-26

申请人： Xiangdong Chen ,  Geng Wang ,  Yujun Li ,  Qiqing Ouyang

发明人： Xiangdong Chen ,  Geng Wang ,  Yujun Li ,  Qiqing Ouyang

IPC分类号： H01L29/94

CPC分类号： H01L29/66181 ,  H01L27/10864

摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.

摘要翻译： 在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。 晶体管栅极被设计代替通道。 用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。 存储节点附近的栅极材料为n型掺杂多晶硅。 位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。 该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

公开(公告)号：US20060237785A1

公开(公告)日：2006-10-26

申请号：US11112820

申请日：2005-04-22

申请人： Meikei Ieong ,  Qiqing Ouyang ,  Kern Rim

发明人： Meikei Ieong ,  Qiqing Ouyang ,  Kern Rim

IPC分类号： H01L29/76

CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.

摘要翻译： 本发明提供CMOS结构，其包括位于旋转的半导体衬底上的至少一个应变pFET，以改善器件性能。 具体地，本发明利用具有（100）晶体取向的含Si半导体衬底，其中衬底旋转约45°，使得CMOS器件沟道沿<100>方向定位。 通过在衬底中形成嵌入的应力阱，或者通过利用嵌入的应力阱的组合，或者通过利用嵌入的应力阱的组合，可以在包括至少pFET和任选的nFET，特别是沟道的CMOS结构上诱导应变， 一个紧张的班轮。 本发明还提供了制造上述半导体结构的方法。

公开(公告)号：US07115965B2

公开(公告)日：2006-10-03

申请号：US10931855

申请日：2004-09-01

申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

IPC分类号： H01L29/70

CPC分类号： H01L29/7317 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0821 ,  H01L29/66265

摘要： The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

摘要翻译： 本发明提供了一种不含杂质掺杂子集电极的“不带集电极的绝缘体上硅”（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在操作时使用背栅极多数载流子积累层作为子集电极。 SOI衬底被偏置，使得积累层形成在第一半导体层的底部。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。 还提供了背栅CMOS装置。