公开(公告)号：US20120286836A1

公开(公告)日：2012-11-15

申请号：US13103571

申请日：2011-05-09

Applicant: Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

Inventor： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H03K3/84

CPC classification number: G01R31/2824

Abstract: A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.

Abstract translation: 用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。 射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。 此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。 另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

公开(公告)号：US08729968B2

公开(公告)日：2014-05-20

申请号：US13103571

申请日：2011-05-09

Applicant: Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

Inventor： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H03L5/00

CPC classification number: G01R31/2824

Abstract: A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.

Abstract translation: 用于测试压控振荡器的内置自检电路包括压控振荡器，具有耦合到压控振荡器的输出的输入的缓冲器和耦合到缓冲器的输出的射频峰值检测器。 射频峰值检测器被配置为从压控振荡器接收交流信号，并且在射频峰值检测器的输出处产生与ac信号成比例的直流值。 此外，当压控振荡器正常工作时，射频峰值检测器的输出产生与来自压控振荡器的ac信号的幅度成比例的直流值。 另一方面，当压控振荡器不能产生交流信号时，射频峰值检测器的输出为零伏特。

公开(公告)号：US08664729B2

公开(公告)日：2014-03-04

申请号：US13325922

申请日：2011-12-14

Applicant: Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

Inventor： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

IPC: H01L27/088

CPC classification number: H01L29/66795 ,  H01L29/42372 ,  H01L29/785

Abstract: Methods and apparatus for reduced gate resistance finFET. A metal gate transistor structure is disclosed including a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Methods for forming the reduced gate finFET are disclosed.

Abstract translation: 降低栅极电阻finFET的方法和装置。 公开了一种金属栅极晶体管结构，其包括形成在半导体衬底上的多个半导体鳍片，所述鳍片平行布置并间隔开; 一个含金属的栅电极，形成在半导体衬底之上，并且覆盖每个半导体鳍片的沟道栅极区域，并且在半导体鳍片之间的半导体衬底上延伸; 覆盖所述栅电极和所述半导体衬底的层间电介质层; 以及多个触点，其布置在所述层间电介质层中并且延伸穿过所述层间电介质层到所述栅电极; 形成在所述层间电介质层上并且由所述多个触点耦合到所述栅电极的低电阻金属带; 其中所述多个触点与所述半导体鳍片的沟道栅极区域间隔开。 公开了形成栅极finFET的方法。

公开(公告)号：US20130154011A1

公开(公告)日：2013-06-20

申请号：US13325922

申请日：2011-12-14

Applicant: Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

Inventor： Chewn-Pu Jou ,  Tzu-Jin Yeh ,  Hsieh-Hung Hsieh

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/42372 ,  H01L29/785

Abstract: Methods and apparatus for reduced gate resistance finFET. A metal gate transistor structure is disclosed including a plurality of semiconductor fins formed over a semiconductor substrate, the fins being arranged in parallel and spaced apart; a metal containing gate electrode formed over the semiconductor substrate and overlying a channel gate region of each of the semiconductor fins, and extending over the semiconductor substrate between the semiconductor fins; an interlevel dielectric layer overlying the gate electrode and the semiconductor substrate; and a plurality of contacts disposed in the interlevel dielectric layer and extending through the interlevel dielectric layer to the gate electrode; a low resistance metal strap formed over the interlevel dielectric layer and coupled to the gate electrode by the plurality of contacts; wherein the plurality of contacts are spaced apart from the channel gate regions of the semiconductor fins. Methods for forming the reduced gate finFET are disclosed.

Abstract translation: 降低栅极电阻finFET的方法和装置。 公开了一种金属栅极晶体管结构，其包括形成在半导体衬底上的多个半导体鳍片，所述鳍片平行布置并间隔开; 一个含金属的栅电极，形成在半导体衬底之上，并且覆盖每个半导体鳍片的沟道栅极区域，并且在半导体鳍片之间的半导体衬底上延伸; 覆盖所述栅电极和所述半导体衬底的层间电介质层; 以及多个触点，其布置在所述层间电介质层中并且延伸穿过所述层间电介质层到所述栅电极; 形成在所述层间电介质层上并且由所述多个触点耦合到所述栅电极的低电阻金属带; 其中所述多个触点与所述半导体鳍片的沟道栅极区域间隔开。 公开了形成栅极finFET的方法。

公开(公告)号：US08334571B2

公开(公告)日：2012-12-18

申请号：US12731562

申请日：2010-03-25

Applicant: Ming-Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

Inventor： Ming-Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H01L23/60 ,  H01L23/64 ,  H01L29/08

CPC classification number: H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.

Abstract translation: ESD保护装置包括设置在形成第一二极管的第二半导体类型的衬底中的第一半导体类型的第一阱。 第二半导体类型的第二阱形成在衬底中以与第一阱形成第二二极管。 第一半导体类型的第一多个掺杂区域形成在第一阱的上表面中。 第二半导体类型的第二多个掺杂区域形成在第一阱的上表面中，其与第一阱形成第三二极管。 多个STI区域形成在第一阱的上表面中。 每个STI区域设置在第一和第二半导体类型的掺杂区域之间。 当在第一或第二多个掺杂区域中的一个处接收ESD电压尖峰时，第三二极管提供电流旁路。

公开(公告)号：US20110260819A1

公开(公告)日：2011-10-27

申请号：US12766970

申请日：2010-04-26

Applicant: Tzu-Jin Yeh ,  Kal-Wen Tan ,  Ming Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

Inventor： Tzu-Jin Yeh ,  Kal-Wen Tan ,  Ming Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H01F21/00

CPC classification number: H01F21/02 ,  H01F21/005 ,  H01F2021/125

Abstract: An integrated tunable inductor includes a primary inductor having a plurality of inductor turns, at least one closed loop eddy current coil proximate the primary inductor, and at least one variable resistor integrated in series with the eddy current coil.

Abstract translation: 集成可调电感器包括具有多个电感线圈的初级电感器，至少一个靠近初级电感器的闭环涡流线圈以及与涡流线圈串联集成的至少一个可变电阻器。

公开(公告)号：US20050023639A1

公开(公告)日：2005-02-03

申请号：US10632456

申请日：2003-07-31

Applicant: Tzu-Jin Yeh ,  Hsien-Chang Wu ,  Ming-Ta Yang ,  Yu-Tai Chia

Inventor： Tzu-Jin Yeh ,  Hsien-Chang Wu ,  Ming-Ta Yang ,  Yu-Tai Chia

IPC: H01L21/02 ,  H01L27/08 ,  H01L29/00

CPC classification number: H01L28/10 ,  H01L27/08

Abstract: An inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type and at least two deep wells of opposite conductivity type in the substrate underneath the track. In another embodiment, an inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type; a shallow trench isolation region formed in the substrate underneath the trace; and at least two deep wells of opposite conductivity type in the substrate underneath the shallow trench isolation region. The present invention also includes methods of manufacturing the aforementioned inductors.

Abstract translation: 集成电路中的电感器包括布置在绝缘层上的导电迹线，绝缘层覆盖在轨道下方的衬底中的第一导电类型的半导体衬底和相反导电类型的至少两个深阱。 在另一个实施例中，集成电路中的电感器包括布置在绝缘层上的导电迹线，绝缘层覆盖在第一导电类型的半导体衬底上; 在轨迹下方的衬底中形成的浅沟槽隔离区域; 以及在浅沟槽隔离区域下方的衬底中具有相反导电类型的至少两个深阱。 本发明还包括制造上述电感器的方法。

公开(公告)号：US20150311159A1

公开(公告)日：2015-10-29

申请号：US14264076

申请日：2014-04-29

Applicant: Hsieh-Hung Hsieh ,  Tzu-Jin Yeh ,  Sa-Lly Liu ,  Tzong-Lin Wu

Inventor： Hsieh-Hung Hsieh ,  Tzu-Jin Yeh ,  Sa-Lly Liu ,  Tzong-Lin Wu

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107

Abstract: An electromagnetic bandgap (EBG) cell comprises a plurality of first conductive line layers beneath a first integrated circuit (IC) die, wherein wires on at least one of the first conductive line layers are each connected to one of a high voltage source and a low voltage source and are oriented to form a first mesh structure at a bottom of the EBG cell. The EBG cell further comprises a pair of through-substrate-vias (TSVs) above the plurality of first conductive line layers, wherein the pair of TSVs penetrate the first IC die and are connected to a high voltage source and a low voltage source, respectively, and a pair of micro bumps above a dielectric layer above the pair of TSVs, wherein the micro bumps connect the TSVs of the first IC die with a plurality of second conductive line layers formed on a second IC die.

Abstract translation: 电磁带隙（EBG）单元包括在第一集成电路（IC）管芯下面的多个第一导线层，其中至少一个第一导线层上的导线各自连接到高电压源和低电压 电压源并且被定向以在EBG电池的底部形成第一网状结构。 EBG单元还包括在多个第一导线层上方的一对穿通基板通孔（TSV），其中该对TSV穿过第一IC管芯并且分别连接到高电压源和低压源 以及在所述一对TSV上方的电介质层上方的一对微凸块，其中所述微凸块将所述第一IC管芯的TSV与形成在第二IC管芯上的​​多个第二导线层连接。

公开(公告)号：US08627253B2

公开(公告)日：2014-01-07

申请号：US12766732

申请日：2010-04-23

Applicant: Tzu-Jin Yeh ,  Kal-Wen Tan ,  Chewn-Pu Jou ,  Sally Liu ,  Fu-Lung Hsueh

Inventor： Tzu-Jin Yeh ,  Kal-Wen Tan ,  Chewn-Pu Jou ,  Sally Liu ,  Fu-Lung Hsueh

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/82

Abstract: In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal.

Abstract translation: 根据实施例，用于衬底噪声分析的方法包括使用基于第一处理器的系统，创建和模拟包括晶体管的多端子模型的电路原理图，然后基于电路原理图中所示的特性创建布局 和仿真结果的模拟。 多端子模型包括源极端子，栅极端子，漏极端子，主体端子和保护环端子。

公开(公告)号：US08451033B2

公开(公告)日：2013-05-28

申请号：US12967160

申请日：2010-12-14

Applicant: Po-Yi Wu ,  Hsieh-Hung Hsieh ,  Ho-Hsiang Chen ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

Inventor： Po-Yi Wu ,  Hsieh-Hung Hsieh ,  Ho-Hsiang Chen ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H03B19/00

CPC classification number: H03B19/00

Abstract: A millimeter-wave wideband frequency doubler stage for use in a distributed frequency doubler includes: a differential input pair of transistors, each transistor having respective gate, drain and source terminals, wherein the source terminals are coupled together to a first power supply node and the drain terminals are coupled together at a first node to a second power supply node; first and second pairs of bandpass gate lines coupled to the gate terminals of the transistors; and a pair of bandpass drain lines coupled to the drain terminals of the transistors.

Abstract translation: 用于分布式倍频器的毫米波宽带倍频器级包括：差分输入对晶体管，每个晶体管具有相应的栅极，漏极和源极端子，其中源极端子耦合到第一电源节点，并且 漏极端子在第一节点耦合到第二电源节点; 耦合到晶体管的栅极端子的第一和第二对带通栅极线; 以及耦合到晶体管的漏极端子的一对带通漏极线。