公开(公告)号：US11683053B2

公开(公告)日：2023-06-20

申请号：US17178604

申请日：2021-02-18

Applicant: KIOXIA CORPORATION

Inventor： Riki Suzuki ,  Toshikatsu Hida ,  Osamu Torii ,  Hiroshi Yao ,  Kiyotaka Iwasaki

IPC: H03M13/00 ,  H03M13/35 ,  G06F11/10 ,  H03M13/29 ,  G06F3/06 ,  G11C29/52 ,  G11C7/10 ,  G11B20/18 ,  G11C29/04

CPC classification number: H03M13/35 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1076 ,  G11C29/52 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2957 ,  G11B20/1833 ,  G11C7/1006 ,  G11C2029/0411

Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.

公开(公告)号：US11561854B2

公开(公告)日：2023-01-24

申请号：US17464552

申请日：2021-09-01

Applicant: KIOXIA CORPORATION

Inventor： Noboru Okamoto ,  Toshikatsu Hida

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/20 ,  G11C16/04

Abstract: A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.

公开(公告)号：US11513682B2

公开(公告)日：2022-11-29

申请号：US17083529

申请日：2020-10-29

Applicant: Kioxia Corporation

Inventor： Hirokuni Yano ,  Shinichi Kanno ,  Toshikatsu Hida ,  Hidenori Matsuzaki ,  Kazuya Kitsunai ,  Shigehiro Asano

IPC: G06F3/06 ,  G11C11/56 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/0866

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.