公开(公告)号：US08624318B2

公开(公告)日：2014-01-07

申请号：US13456634

申请日：2012-04-26

申请人： Zhong-Xiang He ,  Qizhi Liu

发明人： Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L29/775

CPC分类号： H01L29/66977 ,  B82Y10/00 ,  H01L21/76264 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided.

摘要翻译： 半导体电路包括多个半导体器件，每个半导体器件包括具有至少一个电掺杂剂原子并位于绝缘体层上的半导体岛。 每个半导体岛由包括至少一个介电材料部分的电介质材料包封。 导电材料部分，其至少一个邻接两个不同的半导体岛的两个电介质材料部分，直接位于至少一个电介质材料层上。 提供至少一个栅极导体，其覆盖至少两个半导体岛。 跨越半导体岛和导电材料部分之间的电介质材料部分的传导是通过量子隧穿实现的。 导电材料部分和至少一个栅极导体用于形成具有低漏电流的半导体电路。 还提供了用于半导体电路的设计结构。

公开(公告)号：US08592876B2

公开(公告)日：2013-11-26

申请号：US13342689

申请日：2012-01-03

申请人： Hanyi Ding ,  Qizhi Liu ,  Anthony K. Stamper

发明人： Hanyi Ding ,  Qizhi Liu ,  Anthony K. Stamper

IPC分类号： H01L29/80

CPC分类号： H01H1/0036 ,  B81B7/0006 ,  B81B2201/016 ,  G06F17/5063 ,  G06F17/5068 ,  H01P1/127

摘要： A micro-electro-mechanical system (MEMS), methods of forming the MEMS and design structures are provided. The method comprises forming a coplanar waveguide (CPW) comprising a signal electrode and a pair of electrodes on a substrate. The method comprises forming a first sacrificial material over the CPW, and a wiring layer over the first sacrificial material and above the CPW. The method comprises forming a second sacrificial material layer over the wiring layer, and forming insulator material about the first sacrificial material and the second sacrificial material. The method comprises forming at least one vent hole in the insulator material to expose portions of the second sacrificial material, and removing the first and second sacrificial material through the vent hole to form a cavity structure about the wiring layer and which exposes the signal line and pair of electrodes below the wiring layer. The vent hole is sealed with sealing material.

摘要翻译： 提供了微机电系统（MEMS），形成MEMS和设计结构的方法。 该方法包括在衬底上形成包括信号电极和一对电极的共面波导（CPW）。 该方法包括在CPW上形成第一牺牲材料，以及在第一牺牲材料上方和CPW上方的布线层。 该方法包括在布线层上形成第二牺牲材料层，以及围绕第一牺牲材料和第二牺牲材料形成绝缘体材料。 该方法包括在绝缘体材料中形成至少一个通气孔以暴露第二牺牲材料的部分，以及通过通气孔去除第一和第二牺牲材料，以形成围绕布线层的空腔结构，并使信号线和 一对电极在布线层下方。 通气孔用密封材料密封。

公开(公告)号：US08536012B2

公开(公告)日：2013-09-17

申请号：US13177146

申请日：2011-07-06

申请人： Renata Camillo-Castillo ,  Peter B. Gray ,  David L. Harame ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu

发明人： Renata Camillo-Castillo ,  Peter B. Gray ,  David L. Harame ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu

IPC分类号： H01L21/331 ,  H01L21/02

CPC分类号： H01L29/73 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/66272 ,  H01L29/7322

摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.

摘要翻译： 用于制造双极结型晶体管的方法，通过该方法制造的双极结型晶体管以及双极结型晶体管的设计结构。 双极结晶体管包括在本征基极上的电介质层和通过电介质层至少部分地与本征基极分离的外部基极。 发射极开口延伸穿过外部基极和电介质层。 电介质层相对于发射器开口横向凹入以限定内部基极和外部基极之间的腔。 空腔填充有将外部基极和内在基极物理连接在一起的半导体层。

公开(公告)号：US20130134483A1

公开(公告)日：2013-05-30

申请号：US13307412

申请日：2011-11-30

申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC分类号： H01L29/737 ,  H01L21/331 ,  H01L29/73

CPC分类号： H01L29/66234 ,  H01L29/0826 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7371

摘要： Disclosed are a transistor and a method of forming the transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased.

摘要翻译： 公开了晶体管和以缩小的尺寸形成具有凸起的集电极基座的晶体管的方法，以减小基极 - 集电极结电容。 凸起的收集器基座位于基板的顶表面上，垂直延伸穿过绝缘层（未掺杂或低掺杂）在衬底内的子集电极区域上方排列， 收集区域。 本征基层在凸起的收集器基座和介电层之上。 外在基层在本征基层之上。 因此，外部基极层和副集电极区域之间的空间增加。 该增加的空间由电介质材料填充，并且本征基极层和次集电极区域之间的电连接由相对窄的未掺杂或低掺杂的升高的集电极基座提供。 因此，集电极结电容减小，因此最大振荡频率增加。

公开(公告)号：US20130119508A1

公开(公告)日：2013-05-16

申请号：US13294671

申请日：2011-11-11

申请人： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu ,  Ramana M. Malladi ,  John J. Pekarik

发明人： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu ,  Ramana M. Malladi ,  John J. Pekarik

IPC分类号： H01L29/73 ,  G06F17/50 ,  H01L21/331

CPC分类号： H01L29/66303 ,  G06F17/5045 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/7322 ,  H01L29/735

摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process.

摘要翻译： 用于制造双极结型晶体管的方法，双极结型晶体管以及用于双极结型晶体管的设计结构。 双极结晶体管可以包括布置在不同的发射极指中的多个发射极。 形成了覆盖双极结型晶体管的非本征基极层并填充相邻发射极之间的间隙的硅化物层。 发射极侧壁上的非导电间隔物使发射体与硅化物层电绝缘。 发射极延伸通过外部基极层和硅化物层与本征基极层接触。 发射器可以在替代型工艺中使用牺牲发射器基座形成。

公开(公告)号：US20130119434A1

公开(公告)日：2013-05-16

申请号：US13296496

申请日：2011-11-15

申请人： JAMES W. ADKISSON ,  David L. Harame ,  Robert K. Leidy ,  Qizhi Liu

发明人： JAMES W. ADKISSON ,  David L. Harame ,  Robert K. Leidy ,  Qizhi Liu

IPC分类号： H01L29/737 ,  H01L29/73 ,  H01L21/331

CPC分类号： H01L29/732 ,  H01L29/7371

摘要： Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance Cbc. In the embodiments, a collector region is positioned laterally adjacent to a trench isolation region within a substrate. Mask layer(s) cover the trench isolation region and further extend laterally onto the edge portion of the collector region. A first section of an intrinsic base layer is positioned above a center portion of the collector region and a second section of the intrinsic base layer is positioned above the mask layer(s). During processing these mask layer(s) prevent divot formation in the upper corner of the trench isolation region at the isolation region-collector region interface and further limit dopant diffusion from a subsequently formed raised extrinsic base layer into the collector region.

摘要翻译： 公开了晶体管（例如双极结型晶体管（BJT）或异质结双极晶体管（HBT））的实施例以及形成具有集电极区域的晶体管的方法，该集电极区域具有用于还原的基极 - 集电极结电容Cbc的受保护的上边缘部分。 在实施例中，集电极区域位于衬底内侧向与沟槽隔离区域相邻的位置。 掩模层覆盖沟槽隔离区域并且进一步横向延伸到收集器区域的边缘部分上。 本征基极层的第一部分位于集电极区域的中心部分的上方，并且本征基极层的第二部分位于掩模层之上。 在处理期间，这些掩模层防止在隔离区域 - 集电极区界面处的沟槽隔离区的上角部形成裂缝，并且进一步限制从随后形成的凸起的外在基极层到集电极区域的掺杂剂扩散。

公开(公告)号：US07521327B2

公开(公告)日：2009-04-21

申请号：US11378927

申请日：2006-03-17

申请人： Alvin Jose Joseph ,  Qizhi Liu

发明人： Alvin Jose Joseph ,  Qizhi Liu

IPC分类号： H01L21/331

CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/732

摘要： A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.

摘要翻译： 高fT和fmax双极晶体管包括发射极，基极和集电极。 发射器具有延伸超出下部的下部和上部。 基础包括内在基础和外在碱基。 本征基极位于发射极的下部和集电极之间。 外部基极从发射器的下部延伸超过发射器的上部，并且包括从发射器的上部下方延伸并从发射器的上部下方延伸的连续导体。 连续导体提供从底部触点（未示出）到本征基极的低电阻路径。 晶体管可以包括不延伸在发射极的上部下方的第二导体，但是通过外部基极进一步降低电阻。

公开(公告)号：US07491985B2

公开(公告)日：2009-02-17

申请号：US11288843

申请日：2005-11-29

申请人： Peter J. Geiss ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu

发明人： Peter J. Geiss ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu

IPC分类号： H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

CPC分类号： H01L29/0821 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66318

摘要： A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.

摘要翻译： 提供了用于高速BiCMOS应用的异步双极晶体管（HBT），其中通过在器件的子集电极上的浅沟槽隔离区域的下面提供掩埋难熔金属硅化物层来降低集电极电阻Rc。 具体地，本发明的HBT包括至少包括子集电极的基板; 位于子集电极上的埋置难熔金属硅化物层; 以及位于掩埋难熔金属硅化物层的表面上的浅沟槽隔离区域。 本发明还提供一种制造这种HBT的方法。 该方法包括在器件的子集电极上的浅沟槽隔离区域的下面形成埋置难熔金属硅化物。

公开(公告)号：US20080268604A1

公开(公告)日：2008-10-30

申请号：US12128077

申请日：2008-05-28

申请人： Peter J. Geiss ,  Marwan H. Khater ,  Qizhi Liu ,  Randy W. Mann ,  Robert J. Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas D. Stricker

发明人： Peter J. Geiss ,  Marwan H. Khater ,  Qizhi Liu ,  Randy W. Mann ,  Robert J. Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas D. Stricker

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。

公开(公告)号：US20060177986A1

公开(公告)日：2006-08-10

申请号：US11378927

申请日：2006-03-17

申请人： Alvin Joseph ,  Qizhi Liu

发明人： Alvin Joseph ,  Qizhi Liu

IPC分类号： H01L21/8222

CPC分类号： H01L29/66287 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/732

摘要： A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.

摘要翻译： 高电平和高压双极晶体管包括发射极，基极和集电极。 发射器具有延伸超出下部的下部和上部。 基础包括内在基础和外在碱基。 本征基极位于发射极的下部和集电极之间。 外部基极从发射器的下部延伸超过发射器的上部，并且包括从发射器的上部下方延伸并从发射器的上部下方延伸的连续导体。 连续导体提供从底部触点（未示出）到本征基极的低电阻路径。 晶体管可以包括不延伸在发射极的上部下方的第二导体，但是通过外部基极进一步降低电阻。