公开(公告)号：US10478914B2

公开(公告)日：2019-11-19

申请号：US15319097

申请日：2015-05-20

申请人： Naoki Nakagawa ,  Shintaro Suzuki ,  Kenichi Nakano ,  Takuya Fujita ,  Kiyohiro Suzuki ,  Renji Natsume ,  Tatsuro Sugiyama ,  Masazumi Kobayashi

发明人： Naoki Nakagawa ,  Shintaro Suzuki ,  Kenichi Nakano ,  Takuya Fujita ,  Kiyohiro Suzuki ,  Renji Natsume ,  Tatsuro Sugiyama ,  Masazumi Kobayashi

IPC分类号： B23K10/00 ,  B23K15/00 ,  B23K26/21 ,  F16D3/205 ,  F16D3/223 ,  B23K15/04 ,  B23K26/08 ,  B23K33/00 ,  G01N29/04 ,  G01N29/22 ,  G01N29/28 ,  B23K26/282 ,  F16D1/027 ,  F16D3/227 ,  B23K101/04 ,  B23K103/04 ,  B23K103/18

摘要： For butt-welding, which includes bringing joining end surfaces of a cup member and a shaft member into abutment against each other and radiating a high energy intensity beam from a radially outer side, the shaft member has a recess on a radially inner side of the joining end surface to obtain a welded portion having a closed hollow cavity on a radially inner side after butt-welding. The joining end surface (protruding surface) of the cup member protrudes toward a radially inner side with respect to an inner diameter of the joining end surface of the shaft member. With this, a welded portion of an outer joint member of a constant velocity universal joint, which is manufactured by joining the cup member and the shaft member, can be improved in strength and quality.

公开(公告)号：US07847295B2

公开(公告)日：2010-12-07

申请号：US12026794

申请日：2008-02-06

申请人： Hitoshi Nagata ,  Naoki Nakagawa

发明人： Hitoshi Nagata ,  Naoki Nakagawa

IPC分类号： H01L27/14

CPC分类号： H01L29/78606 ,  H01L27/1248 ,  H01L29/66765

摘要： A thin film transistor includes a gate electrode, a gate insulating film formed to cover the gate electrode, a semiconductor layer including a channel region formed over the gate electrode, a source electrode and a drain electrode including a region connected to the semiconductor layer, where at least a part of the region is overlapped with the gate electrode, an upper insulating film formed to cover the semiconductor layer, the source electrode and the drain electrode, where the upper insulating film is directly in contact with the channel region of the semiconductor layer and discharges moisture by a heat treatment and a second upper insulating film formed to cover the first protective film and suppress moisture out-diffusion.

摘要翻译： 薄膜晶体管包括栅电极，形成为覆盖栅电极的栅绝缘膜，包括形成在栅电极上的沟道区的半导体层，源电极和漏电极，其包括连接到半导体层的区域，其中 所述区域的至少一部分与所述栅电极重叠，形成为覆盖所述半导体层，所述源电极和漏电极的上绝缘膜，所述上绝缘膜与所述半导体层的沟道区域直接接触 并通过热处理进行水分排出和形成为覆盖第一保护膜的第二上部绝缘膜，并抑制水分向外扩散。

公开(公告)号：US20100295256A1

公开(公告)日：2010-11-25

申请号：US12863652

申请日：2009-01-08

申请人： Tatsuo Nakajima ,  Naoki Nakagawa ,  Seiji Katayama ,  Yousuke Kawahito

发明人： Tatsuo Nakajima ,  Naoki Nakagawa ,  Seiji Katayama ,  Yousuke Kawahito

IPC分类号： F16J15/52 ,  B32B37/06

CPC分类号： F16D3/845 ,  F16D3/223 ,  F16D3/227 ,  F16D2003/22316 ,  F16D2250/00 ,  F16D2300/12 ,  F16J3/042

摘要： Provided is a mounting structure for a boot for a constant velocity universal joint, which is capable of ensuring a stable sealing performance at low cost. The resin boot (1) for the constant velocity universal joint includes a smaller-diameter end portion (2) and a larger-diameter end portion (3), each of which has a cylindrical shape. The smaller-diameter end portion (2) of the boot (1) is fixed to a shaft (17) constituting an inner member, and the larger-diameter end portion (3) is fixed to an outer joint member (11) serving as an outer member. An inner peripheral surface of the smaller-diameter end portion (2) of the boot (1) is integrally bonded to an outer peripheral surface of a boot-mounting portion (18) of the shaft (17) in an abutting state due to a physical interaction between a resin constituting the boot (1) and a metal constituting the shaft (17). Further, an inner peripheral surface of the larger-diameter end portion (3) of the boot (1) is integrally bonded to an outer peripheral surface of a boot-mounting portion (19) of the outer joint member (11) in an abutting state due to the physical interaction between the resin constituting the boot (1) and the metal constituting the outer joint member (11).

摘要翻译： 本发明提供一种用于等速万向接头的保护罩的安装结构，其能够以低成本确保稳定的密封性能。 用于等速万向接头的树脂罩（1）包括小直径端部（2）和较大直径的端部（3），每个都具有圆柱形形状。 靴子（1）的小直径端部（2）固定在构成内部构件的轴（17）上，大直径端部（3）固定在作为 外部成员。 靴子（1）的较小直径的端部（2）的内周面由于在一个邻接的状态下一体地结合到轴（17）的靴子安装部分（18）的外周表面 构成靴子（1）的树脂与构成轴（17）的金属之间的物理相互作用。 此外，所述护罩（1）的所述大直径端部（3）的内周面与所述外侧接头构件（11）的护罩安装部（19）的外周面一体地接合， 由于构成靴子（1）的树脂与构成外侧接头构件（11）的金属之间的物理相互作用而产生的状态。

公开(公告)号：US20100253647A1

公开(公告)日：2010-10-07

申请号：US12740124

申请日：2008-11-10

申请人： Masafumi Agari ,  Naoki Nakagawa ,  Seiichiro Mori ,  Hiroyuki Murai

发明人： Masafumi Agari ,  Naoki Nakagawa ,  Seiichiro Mori ,  Hiroyuki Murai

IPC分类号： G06F3/045

CPC分类号： G06F3/044 ,  G06F3/0416

摘要： A touch panel capable of calculating touch position coordinates of an indicator with high accuracy in a desired detection time even if a large number of detection wire groups are provided. An oscillator circuit selects one of detection wires selected by a circuit or the like according to a command from a detection control circuit and oscillates. A circuit counts an output signal from the oscillator circuit up to a first count value. A circuit measures a period of the count. A circuit determines that there is a touch when it detects the detection wire of which the measured period is equal to or higher than a threshold value and sends the detection wire giving a maximum value equal to or higher than the threshold value to a circuit as a touch detection wire. The circuit causes the circuit or the like to select the touch detection wire and the detection wires adjacent thereto on both sides, the circuit counts up until the count value becomes a second count value larger than the first count value, and the circuit measures the count period. The circuit performs interpolation on the basis of the count value obtained by subtracting a background capacitance value from a measured value obtained by the circuit, to thereby determine the touch coordinates.

摘要翻译： 即使提供了大量检测线组，能够在期望的检测时间内高精度地计算指示器的触摸位置坐标的触摸面板。 振荡电路根据来自检测控制电路的指令，选择由电路等选择的检测线之一并振荡。 电路将来自振荡器电路的输出信号计数到第一计数值。 电路测量一段时间。 电路确定当检测到测量周期等于或高于阈值的检测线时有触摸，并将给出等于或高于阈值的最大值的检测线发送到电路作为 触摸检测线。 电路使电路等在两侧选择触摸检测线及与其相邻的检测线，电路向上计数，直到计数值变为比第一计数值大的第二计数值，并且电路测量计数 期。 电路根据通过从电路获得的测量值减去背景电容值而得到的计数值进行内插，从而确定触摸坐标。

公开(公告)号：US07612378B2

公开(公告)日：2009-11-03

申请号：US11376414

申请日：2006-03-16

申请人： Yoshihiko Toyoda ,  Naoki Nakagawa ,  Taro Yoshino

发明人： Yoshihiko Toyoda ,  Naoki Nakagawa ,  Taro Yoshino

IPC分类号： H01L29/08

CPC分类号： H01L27/1214 ,  H01L27/3244 ,  H01L29/78624 ,  H01L2029/7863

摘要： A silicon nitride film and a silicon oxide film are formed on a glass substrate. On the silicon oxide film is formed a thin film transistor including a source region, a drain region, a channel region having a predetermined channel length, an LDD region and GOLD region having an impurity concentration higher than the impurity concentration of the channel region and lower than the impurity concentration of the source and drain regions, a gate insulation film, and a gate electrode. The gate electrode is formed to overlap in plane with the channel region and the GOLD region. Accordingly, a semiconductor device and an image display apparatus directed to improving source-drain breakdown voltage are obtained.

摘要翻译： 在玻璃基板上形成氮化硅膜和氧化硅膜。 在氧化硅膜上形成薄膜晶体管，其包括源极区，漏极区，具有预定沟道长度的沟道区，LDD区和杂质浓度高于沟道区的杂质浓度的GOLD区， 比源极和漏极区域的杂质浓度，栅极绝缘膜和栅极电极。 栅电极形成为与沟道区域和GOLD区域平面重叠。 因此，获得了旨在提高源极 - 漏极击穿电压的半导体器件和图像显示装置。

公开(公告)号：US07541646B2

公开(公告)日：2009-06-02

申请号：US11673773

申请日：2007-02-12

申请人： Hitoshi Nagata ,  Takao Sakamoto ,  Naoki Nakagawa

发明人： Hitoshi Nagata ,  Takao Sakamoto ,  Naoki Nakagawa

IPC分类号： H01L21/84

CPC分类号： H01L29/4908 ,  H01L27/1248 ,  H01L29/66757 ,  H01L29/78636

摘要： A thin film transistor device according to an embodiment of the invention includes: a thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating layer, and a gate electrode formed on an insulating substrate; an interlayer insulating layer covering the thin film transistor; a line electrically connected with the source region, the drain region, and the gate electrode through a contact hole formed in the interlayer insulating layer; a first upper insulating layer covering the line and the interlayer insulating layer and smoothing out stepped portions of the line and irregularities of a surface of the interlayer insulating layer; and a second upper insulating layer covering the first upper insulating layer, the second upper insulating layer having a hydrogen diffusion coefficient smaller than a hydrogen diffusion coefficient of the first upper insulating layer.

摘要翻译： 根据本发明实施例的薄膜晶体管器件包括：薄膜晶体管，其具有包括源极区，漏极区和沟道区的硅层，栅极绝缘层和形成在绝缘基板上的栅电极 ; 覆盖薄膜晶体管的层间绝缘层; 通过形成在所述层间绝缘层中的接触孔与所述源极区，所述漏极区和所述栅电极电连接的线; 覆盖所述线和所述层间绝缘层的第一上绝缘层，并平滑所述线的台阶部分和所述层间绝缘层的表面的不规则性; 以及覆盖所述第一上绝缘层的第二上绝缘层，所述第二上绝缘层的氢扩散系数小于所述第一上绝缘层的氢扩散系数。

公开(公告)号：US20070210353A1

公开(公告)日：2007-09-13

申请号：US11673773

申请日：2007-02-12

申请人： Hitoshi NAGATA ,  Takao Sakamoto ,  Naoki Nakagawa

发明人： Hitoshi NAGATA ,  Takao Sakamoto ,  Naoki Nakagawa

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L29/4908 ,  H01L27/1248 ,  H01L29/66757 ,  H01L29/78636

摘要： A thin film transistor device according to an embodiment of the invention includes: a thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating layer, and a gate electrode formed on an insulating substrate; an interlayer insulating layer covering the thin film transistor; a line electrically connected with the source region, the drain region, and the gate electrode through a contact hole formed in the interlayer insulating layer; a first upper insulating layer covering the line and the interlayer insulating layer and smoothing out stepped portions of the line and irregularities of a surface of the interlayer insulating layer; and a second upper insulating layer covering the first upper insulating layer, the second upper insulating layer having a hydrogen diffusion coefficient smaller than a hydrogen diffusion coefficient of the first upper insulating layer.

摘要翻译： 根据本发明实施例的薄膜晶体管器件包括：薄膜晶体管，其具有包括源极区，漏极区和沟道区的硅层，栅极绝缘层和形成在绝缘基板上的栅电极 ; 覆盖薄膜晶体管的层间绝缘层; 通过形成在所述层间绝缘层中的接触孔与所述源极区，所述漏极区和所述栅电极电连接的线; 覆盖所述线和所述层间绝缘层的第一上绝缘层，并平滑所述线的台阶部分和所述层间绝缘层的表面的不规则性; 以及覆盖所述第一上绝缘层的第二上绝缘层，所述第二上绝缘层的氢扩散系数小于所述第一上绝缘层的氢扩散系数。

公开(公告)号：US07262433B2

公开(公告)日：2007-08-28

申请号：US11137660

申请日：2005-05-26

申请人： Kazuyuki Sugahara ,  Naoki Nakagawa ,  Yoshihiko Toyoda ,  Takao Sakamoto

发明人： Kazuyuki Sugahara ,  Naoki Nakagawa ,  Yoshihiko Toyoda ,  Takao Sakamoto

IPC分类号： H01L27/12

CPC分类号： H01L27/1222 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/78621 ,  H01L29/78627

摘要： A first thin film transistor including a gate electrode, a source region, a drain region, a GOLD region, and a channel region is formed at a first region at a TFT array substrate. A second thin film transistor including a gate electrode, a source region, drain region, a GOLD region, and a channel region is formed at a second region. The GOLD length (0.5 μm) of the GOLD region of the second thin film transistor is set shorter than the GOLD length (1.5 μm) of the GOLD region of the first thin film transistor. Accordingly, a semiconductor device directed to reducing the area occupied by semiconductor elements is obtained.

摘要翻译： 在TFT阵列基板的第一区域形成包括栅极，源极区，漏极区，GOLD区和沟道区的第一薄膜晶体管。 在第二区域形成包括栅电极，源极区，漏极区，GOLD区和沟道区的第二薄膜晶体管。 第二薄膜晶体管的GOLD区域的GOLD长度（0.5μm）被设定为比第一薄膜晶体管的GOLD区域的GOLD长度（1.5μm）短。 因此，获得了旨在减小半导体元件所占的面积的半导体器件。

公开(公告)号：US07151675B2

公开(公告)日：2006-12-19

申请号：US10639464

申请日：2003-08-13

申请人： Yuichiro Murata ,  Naoki Nakagawa

发明人： Yuichiro Murata ,  Naoki Nakagawa

IPC分类号： H01R12/16

CPC分类号： H05K1/14 ,  H05K1/023 ,  H05K1/167 ,  H05K2201/044 ,  H05K2201/10022

摘要： A multi-pin connector for connecting a signal line on a backboard side and a signal line on a daughter board side has open pins where the signal lines are not connected. In order to prevent transmission loss on the signal lines caused by these open pins, terminating resistances are connected to both ends of the open pins, and ends of the terminating resistances opposite to the open pins are connected to ground or to a power supply.

摘要翻译： 用于连接背板侧的信号线和子板侧的信号线的多针连接器具有未连接信号线的开路引脚。 为了防止由这些开放引脚引起的信号线上的传输损耗，端接电阻连接到开放引脚的两端，并且与开路引脚相反的端接电阻的端部连接到地或电源。

公开(公告)号：US20050148425A1

公开(公告)日：2005-07-07

申请号：US11029411

申请日：2005-01-06

申请人： Naoki Nakagawa ,  Masaharu Hori ,  Soichi Yagi

发明人： Naoki Nakagawa ,  Masaharu Hori ,  Soichi Yagi

IPC分类号： F03D11/02 ,  F03D11/00 ,  F16C19/28 ,  F16C33/34 ,  F16H1/28 ,  F16H37/04 ,  F16H57/021 ,  F16H13/06

CPC分类号： F16C19/28 ,  F03D80/70 ,  F16C19/505 ,  F16C33/34 ,  F16C2240/40 ,  F16C2360/31 ,  F16C2361/61 ,  F16H2057/085 ,  Y02E10/722

摘要： There is provided a cylindrical roller bearing (1) which includes an inner race (2), an outer race (3) and first, second and third rows of rollers (4A, 4B and 4C) accommodated within an annular bearing space delimited between the inner and outer races (2 and 3) with the second or intermediate row of the rollers (4B) positioned between the first and third rows of the rollers (4A and 4C). The rollers (4A and 4C) of the first and third rows have respective lengths (LA and LC) greater than the length (LB) of the rollers (4B) of the second row.

摘要翻译： 提供一种圆柱滚子轴承（1），其包括内座圈（2），外座圈（3）和容纳在环形轴承空间内的第一，第二和第三排滚子（4A，4B和4C） 在第一和第三排辊（4A和4C）之间，定位在内圈和外圈（2和3）之间，第二或第二排辊（4B）。 第一和第三排的辊子（4A和4C）具有大于长度（L B＆lt; B＆gt; / SUB>）的第二排的辊（4B）。