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    Metal Oxide Semiconductor (MOS) Transistors Having Three Dimensional Channels
    31.
    发明申请
    Metal Oxide Semiconductor (MOS) Transistors Having Three Dimensional Channels 有权
    具有三维通道的金属氧化物半导体（MOS）晶体管

    公开(公告)号：US20080001218A1

    公开(公告)日：2008-01-03

    申请号：US11854734

    申请日：2007-09-13

    申请人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    发明人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7842

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.

    摘要翻译： 金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。 第一和第二沟道区设置在源区和漏区之间。 沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。 第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。 在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

    SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES AND SEMICONDUCTOR DEVICES USING VOID SPACES
    32.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES AND SEMICONDUCTOR DEVICES USING VOID SPACES 审中-公开
    半导体绝缘体（SOI）衬底和使用空隙的半导体器件

    公开(公告)号：US20070257312A1

    公开(公告)日：2007-11-08

    申请号：US11774240

    申请日：2007-07-06

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78603

    摘要： An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.

    摘要翻译： 通过在其上提供具有牺牲层的衬底，在远离衬底的牺牲层上的有源半导体层和沿着有源半导体层和牺牲层的至少两侧延伸的支撑层来制造SOI衬底 衬底，并且暴露出牺牲层的至少一侧。 牺牲层中的至少一部分被蚀刻穿过其至少一侧，其被支撑层暴露以在衬底和有源半导体层之间形成空隙，使得有源半导体层以间隔的关系支撑 通过支撑层从衬底。 空隙空间可以至少部分地填充有绝缘体衬里。

    Methods of forming metal oxide semiconductor (MOS) transistors having three dimensional channels
    33.
    发明授权
    Methods of forming metal oxide semiconductor (MOS) transistors having three dimensional channels 有权
    形成具有三维通道的金属氧化物半导体（MOS）晶体管的方法

    公开(公告)号：US07285466B2

    公开(公告)日：2007-10-23

    申请号：US10909471

    申请日：2004-08-02

    申请人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    发明人： Sung-Min Kim ,  Dong-Won Kim ,  Eun-Jung Yun ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Hye-Jin Cho

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823885 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7842

    摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.

    摘要翻译： 金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。 第一和第二沟道区设置在源区和漏区之间。 沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。 第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。 在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

    SEMICONDUCTOR DEVICE HAVING TWO DIFFERENT OPERATION MODES EMPLOYING AN ASYMMETRICAL BURIED INSULATING LAYER AND METHOD FOR FABRICATING THE SAME
    34.
    发明申请
    SEMICONDUCTOR DEVICE HAVING TWO DIFFERENT OPERATION MODES EMPLOYING AN ASYMMETRICAL BURIED INSULATING LAYER AND METHOD FOR FABRICATING THE SAME 审中-公开
    具有使用不对称的绝缘绝缘层的两种不同操作模式的半导体器件及其制造方法

    公开(公告)号：US20070184611A1

    公开(公告)日：2007-08-09

    申请号：US11696132

    申请日：2007-04-03

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10802 ,  H01L27/0214 ,  H01L27/10873 ,  H01L29/7841 ,  H01L29/78612

    摘要： According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.

    摘要翻译： 根据一些实施例，半导体器件包括下半导体衬底，上硅图案和MOS晶体管。 MOS晶体管包括形成在上硅图案内的主体区域和由身体区域分离的源极/漏极区域。 掩埋绝缘层插入在下半导体衬底和上硅图案之间。 穿通插塞穿透埋入的绝缘层并且电连接体区域与下半导体衬底，穿通插塞比另一个源极/漏极区域更靠近源极/漏极区域之一。 当源极电压施加到源极/漏极区域之一时，贯通插塞的上表面的至少一部分位于耗尽层的外侧，并且当通过插塞的上表面位于耗尽层内时， 漏极电压施加到该区域。

    Stacked integrated circuit device including multiple substrates and method of manufacturing the same
    36.
    发明申请
    Stacked integrated circuit device including multiple substrates and method of manufacturing the same 审中-公开
    包括多个基板的堆叠集成电路器件及其制造方法

    公开(公告)号：US20050110159A1

    公开(公告)日：2005-05-26

    申请号：US10977702

    申请日：2004-10-28

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

    IPC分类号： H01L23/12 ,  H01L21/762 ,  H01L21/822 ,  H01L25/065 ,  H01L27/06 ,  H01L29/04

    CPC分类号： H01L21/76251 ,  H01L21/8221 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a stacked integrated circuit device including multiple substrates and a method of manufacturing the same. A first integrated circuit substrate, a first integrated circuit formed on the first integrated circuit substrate, and a first passivation insulating layer are sequentially formed. Then, wafer bonding technique for forming an SOI substrate is used, thereby forming a second integrated circuit substrate on the first passivation insulating layer. While forming a second integrated circuit on the second integrated circuit substrate, at least one device-connecting interconnect electrically connects the first and second Integrated circuits and penetrates the second integrated circuit substrate and the first passivation layer. A second passivation insulating layer is formed on an upper surface of the second integrated circuit.

    摘要翻译： 提供了包括多个基板的堆叠集成电路器件及其制造方法。 依次形成第一集成电路基板，形成在第一集成电路基板上的第一集成电路和第一钝化绝缘层。 然后，使用用于形成SOI衬底的晶片接合技术，从而在第一钝化绝缘层上形成第二集成电路衬底。 当在第二集成电路衬底上形成第二集成电路时，至少一个器件连接互连电连接第一和第二集成电路并且穿透第二集成电路衬底和第一钝化层。 第二钝化绝缘层形成在第二集成电路的上表面上。

    Semiconductor devices having a field effect transistor and methods of fabricating the same
    40.
    发明授权
    Semiconductor devices having a field effect transistor and methods of fabricating the same 有权
    具有场效应晶体管的半导体器件及其制造方法

    公开(公告)号：US07510932B2

    公开(公告)日：2009-03-31

    申请号：US11764751

    申请日：2007-06-18

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Jeong-Dong Choe

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Jeong-Dong Choe

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78687 ,  Y10S438/933

    摘要： A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. A support pattern is preferably interposed between the device active pattern and the substrate. The support pattern can be disposed under the gate electrode. A filling insulation pattern is preferably disposed between the device active pattern and the filling insulation pattern. The filling insulation pattern may be disposed under the source/drain region. A device active pattern under the gate electrode is preferably formed of a strained silicon having a lattice width wider than a silicon lattice.

    摘要翻译： 提供具有场效应晶体管的半导体器件及其形成方法。 半导体器件优选地包括设置在衬底的预定区域上的器件有源图案。 栅电极优选地跨过器件有源图案，由栅极绝缘层插入。 支撑图案优选地插入在器件活性图案和基底之间。 支撑图案可以设置在栅电极下方。 填充绝缘图案优选地设置在装置活性图案和填充绝缘图案之间。 填充绝缘图案可以设置在源极/漏极区域下方。 栅电极下方的器件有源图案优选由具有比硅晶格宽的晶格宽度的应变硅形成。