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    Nested wrap-around memory access with fixed offset
    31.
    发明授权
    Nested wrap-around memory access with fixed offset 有权

    公开(公告)号：US10162751B2

    公开(公告)日：2018-12-25

    申请号：US15139252

    申请日：2016-04-26

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang

    IPC: G06F12/06

    Abstract: A nested wrap-around technology includes an address counter and associated logic for generating addresses to perform a nested wrap-around access operation. The nested wrap-around access operation may be a read or a write operation. A wrap-around section length and a wrap-around count define a wrap-around block. A wrap starting address, initially set to a supplied start address, is offset from a lower boundary of a wrap-around section. Access starts at a wrap starting address and proceeds in a wrap-around manner within a wrap-around section. After access of the address immediately preceding the wrap starting address, the wrap starting address is incremented by the wrap-around section length, or, if the wrap-around section is the last one in the wrap-around block, the wrap starting address is set to the lower boundary of the wrap-around block plus the offset. Access continues until a termination event.

    ECC method for flash memory
    32.
    发明授权
    ECC method for flash memory 有权
    闪存的ECC方法

    公开(公告)号：US09535785B2

    公开(公告)日：2017-01-03

    申请号：US14158613

    申请日：2014-01-17

    Applicant: Macronix International Co., Ltd.

    Inventor： Nai-Ping Kuo ,  Shih-Chang Huang ,  Chin-Hung Chang ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC: G06F11/10 ,  G11C16/34

    CPC classification number: G06F11/1048 ,  G06F2212/1036 ,  G11C16/3436

    Abstract: A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.

    Abstract translation: 提供了一种操作存储数据集的存储器和数据集的ECC的方法。 如果存储新数据的多个可寻址段和先前在数据集中编程的数据包括至少预定数量的可寻址段，则该方法包括在将新数据写入数据集时，计算和存储ECC。 该方法包括使用ECC和从ECC导出的第一附加ECC比特来存储是否启用或禁止使用ECC的指示。 该方法包括从数据集读取包括ECC的扩展ECC和从ECC导出的第一附加ECC位，以及根据为数据集存储的指示启用或禁用ECC的使用。 该方法包括使用所述指示和第二附加ECC位使能ECC空白数据集。

    INPUT PIN CONTROL
    33.
    发明申请
    INPUT PIN CONTROL 有权
    输入PIN控制

    公开(公告)号：US20150323946A1

    公开(公告)日：2015-11-12

    申请号：US14274237

    申请日：2014-05-09

    Applicant: Macronix International Co., Ltd.

    Inventor： Kuen-Long Chang ,  Ken-Hui Chen ,  Chin-Hung Chang ,  Chao-Hsin Lin

    IPC: G05F1/46

    CPC classification number: G05F1/46 ,  G05F1/468 ,  H03K17/22

    Abstract: An integrated circuit device includes a pad adapted to receive a signal from an external driver. A state register is programmed with a state that indicates a voltage level to set for the pad during initialization of circuitry on the integrated circuit device responsive to the state for the pad. The voltage level may correspond to a logic low level or a logic high level. A voltage holding circuit is coupled to the pad and the state register, and is configured to force the pad to the voltage level in response to an event that causes the initialization.

    Abstract translation: 集成电路器件包括适于从外部驱动器接收信号的焊盘。 状态寄存器被编程为响应于该焊盘的状态而指示在集成电路器件的电路初始化期间为焊盘设置的电压电平的状态。 电压电平可以对应于逻辑低电平或逻辑高电平。 电压保持电路耦合到焊盘和状态寄存器，并且被配置为响应于引起初始化的事件而迫使焊盘达到电压电平。

    ECC METHOD FOR FLASH MEMORY
    35.
    发明申请
    ECC METHOD FOR FLASH MEMORY 有权
    闪存存储器的ECC方法

    公开(公告)号：US20150205665A1

    公开(公告)日：2015-07-23

    申请号：US14158613

    申请日：2014-01-17

    Applicant: Macronix International Co., Ltd.

    Inventor： Nai-Ping Kuo ,  Shih-Chang Huang ,  Chin-Hung Chang ,  Ken-Hui Chen ,  Kuen-Long Chang ,  Chun-Hsiung Hung

    IPC: G06F11/10

    CPC classification number: G06F11/1048 ,  G06F2212/1036 ,  G11C16/3436

    Abstract: A method of operating a memory storing data sets, and ECCs for the data sets is provided. The method includes when writing new data in a data set, computing and storing an ECC, if a number of addressable segments storing the new data and data previously programmed in the data set includes at least a predetermined number of addressable segments. The method includes storing indications for whether to enable or disable use of the ECCs, using the ECC and a first additional ECC bit derived from the ECC. The method includes reading from a data set an extended ECC including an ECC and a first additional ECC bit derived from the ECC, and enabling or disabling use of the ECC according to the indications stored for the data set. The method includes enabling use of ECCs for blank data sets, using the indications and a second additional ECC bit.

    Abstract translation: 提供了一种操作存储数据集的存储器和数据集的ECC的方法。 如果存储新数据的多个可寻址段和先前在数据集中编程的数据包括至少预定数量的可寻址段，则该方法包括在将新数据写入数据集时，计算和存储ECC。 该方法包括使用ECC和从ECC导出的第一附加ECC比特来存储是否启用或禁止使用ECC的指示。 该方法包括从数据集读取包括ECC的扩展ECC和从ECC导出的第一附加ECC位，以及根据为数据集存储的指示启用或禁用ECC的使用。 该方法包括使用所述指示和第二附加ECC位使能ECC空白数据集。

    MANAGING CONTENT ADDRESSABLE MEMORY DEVICES
    37.
    发明公开
    MANAGING CONTENT ADDRESSABLE MEMORY DEVICES 审中-公开

    公开(公告)号：US20240118806A1

    公开(公告)日：2024-04-11

    申请号：US17961176

    申请日：2022-10-06

    Applicant: Macronix International Co., Ltd.

    Inventor： Chin-Hung Chang ,  Ken-Hui Chen ,  Chun-Hsiung Hung

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679

    Abstract: Systems, devices, methods, and circuits for managing content addressable memory (CAM) devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in memory cells, and a circuitry coupled to the memory cell array and configured to execute a search operation in the memory cell array according to a search instruction. The search instruction includes at least one of search data or an option code, and the option code specifies, for the search operation, at least one of a search length or a search depth.

    MANAGING TAMPER DETECTIONS IN SECURE MEMORY DEVICES
    40.
    发明申请
    MANAGING TAMPER DETECTIONS IN SECURE MEMORY DEVICES 有权

    公开(公告)号：US20210342065A1

    公开(公告)日：2021-11-04

    申请号：US16862129

    申请日：2020-04-29

    Applicant: Macronix International Co., Ltd.

    Inventor： Chin-Hung Chang ,  Chia-Feng Cheng

    IPC: G06F3/06

    Abstract: Systems, methods, circuits, devices, and apparatus including computer-readable mediums for managing tamper detections in secure memory devices. In one aspect, a secure memory device includes: a memory cell array, one or more tamper detectors each configured to detect a respective type of tamper event on at least part of the secure memory device, and a tamper detection status register storing one or more values each indicating a tamper detection status detected by a corresponding tamper detector. The secure memory device can include a command interface coupled to the tamper detection status register and configured to output the values stored in the tamper detection status register when receiving a trigger. The secure memory device can also include an output pin coupled to the tamper detection status register and be configured to automatically output the values stored in the tamper detection status register via the output pin.

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