公开(公告)号：US20240386923A1

公开(公告)日：2024-11-21

申请号：US18789540

申请日：2024-07-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  G11C15/04

Abstract: A memory array is arranged to store data words in respective sets of TCAM cells, where each TCAM cell is configured to store ternary states of a bit of the stored word. A circuit to select a set of TCAM cells in the set of TCAM cells, such as decoders and drivers for word lines, bit lines, block select gates. A circuit to apply an input search word to the TCAM cells in the selected set of TCAM cells, such as a search word buffer or driver on one of word lines or bit lines for the array. A circuit to generate an output indicating similarity of the stored word in the selected set of TCAM cells to the input search word, based on mismatch or possible mismatch of more than one bit of the search word.

公开(公告)号：US20240021224A1

公开(公告)日：2024-01-18

申请号：US17866958

申请日：2022-07-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/08 ,  G11C15/04

CPC classification number: G11C7/1096 ,  G11C7/1069 ,  G11C7/12 ,  G11C8/08 ,  G11C15/04

Abstract: A memory array is arranged to store data words in respective sets of TCAM cells, where each TCAM cell is configured to store ternary states of a bit of the stored word. A circuit to select a set of TCAM cells in the set of TCAM cells, such as decoders and drivers for word lines, bit lines, block select gates. A circuit to apply an input search word to the TCAM cells in the selected set of TCAM cells, such as a search word buffer or driver on one of word lines or bit lines for the array. A circuit to generate an output indicating similarity of the stored word in the selected set of TCAM cells to the input search word, based on mismatch or possible mismatch of more than one bit of the search word.

公开(公告)号：US20220366987A1

公开(公告)日：2022-11-17

申请号：US17321670

申请日：2021-05-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE

IPC: G11C16/08 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device and an operation method thereof are provided. The memory device comprises: a memory array including a plurality of memory cells; a first local signal line decoder coupled to the memory array; a second local signal line decoder coupled to the memory array; and a controller coupled to and controlling the memory array, the first local signal line decoder and the second local signal line decoder, wherein in programming, a threshold voltage distribution of the memory cells is lower than a read voltage; and in erase, the threshold voltage distribution of the memory cells is higher than the read voltage.

公开(公告)号：US20220254799A1

公开(公告)日：2022-08-11

申请号：US17495826

申请日：2021-10-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE ,  Cheng-Lin SUNG ,  Wei-Chen CHEN

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor device is provided. The semiconductor device includes a first vertical stack, a first vertical channel line, a first data storage structure, and a first gate dielectric structure. The first vertical stack includes a first conductive line and a second conductive line. The first vertical channel line vertically passes through the first conductive line and the second conductive line, and the first vertical channel line is a P-type channel. The first data storage structure is disposed between the first conductive line and the first vertical channel line. The first gate dielectric structure is disposed between the second conductive line and the first vertical channel line.

公开(公告)号：US20220231041A1

公开(公告)日：2022-07-21

申请号：US17149782

申请日：2021-01-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen CHEN ,  Hang-Ting LUE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/10

Abstract: A memory device includes a source element, a drain element, channel layers, control electrode layers, and a memory layer. The channel layers are individually electrically connected between the source element and the drain element. Memory cells are defined in the memory layer between the control electrode layers and the channel layers.

公开(公告)号：US20210242347A1

公开(公告)日：2021-08-05

申请号：US16877518

申请日：2020-05-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Lin SUNG ,  Pei-Ying DU ,  Hang-Ting LUE

IPC: H01L29/788 ,  H01L29/792 ,  G11C11/56

Abstract: A multi-gate transistor includes; a doped drain region; a doped source region; a gate group including a first gate and a second gate; a channel, the doped drain region and the doped source region being on respective two sides of the channel; and an interlayer, formed between the channel and the gate group, wherein a first gate voltage and a second gate voltage are applied to the first gate and the second gate of the gate group, respectively, the channel is induced as at least a P sub-channel and at least an N sub-channel and the multi-gate transistor equivalently behaves as a PNPN structure.

公开(公告)号：US20180102177A1

公开(公告)日：2018-04-12

申请号：US15290376

申请日：2016-10-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chen-Jun WU ,  Chih-Chang Hsieh ,  Tzu-Hsuan Hsu ,  Hang-Ting LUE

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3413 ,  G11C2211/562 ,  G11C2211/5648

Abstract: A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the first and second stacks. In a programming order the final program stage S3 is applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i−1). The intermediate program stage S2 is applied only to memory cells for which the preliminary program stage S1 has already been applied to the cells in any neighboring levels (levels i+1 and i−1).

公开(公告)号：US20160267995A1

公开(公告)日：2016-09-15

申请号：US14643907

申请日：2015-03-10

Applicant: Macronix International Co., Ltd.

Inventor： Kuo-Pin CHANG ,  Hang-Ting LUE ,  Wen-Wei YEH

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3472

Abstract: A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset of the set of word lines in the selected block to induce tunneling in memory cells coupled to the selected subset. Word line-side inhibit voltages are applied to an unselected subset of the set of word lines in the selected block to inhibit tunneling in memory cells coupled to the unselected subset.

Abstract translation: 提供了一种用于操作包括多个存储单元块的NAND阵列的方法。 存储单元块包括多个具有第一串选择开关和第二串选择开关之间的通道线的NAND串。 多个NAND串在第一和第二串选择开关之间共享一组字线。 通道侧擦除电压通过所选块中的第一串选择开关施加到通道线。 字线侧擦除电压被施加到所选块中所选择的字线集合的选定子集，以诱导耦合到所选子集的存储器单元中的隧穿。 字线侧抑制电压被施加到所选块中的字线组的未选择子集，以抑制耦合到未选择子集的存储器单元中的隧穿。