公开(公告)号：US20230095392A1

公开(公告)日：2023-03-30

申请号：US18073366

申请日：2022-12-01

Applicant: MACRONIX International Co., Ltd.

Inventor： Feng-Min Lee ,  Po-Hao Tseng ,  Yu-Hsuan Lin ,  Ming-Hsiu Lee

IPC: G11C16/30 ,  H01L29/788 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  H01L29/792 ,  H01L29/423 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11529 ,  G11C11/56 ,  H01L27/1157

Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.

公开(公告)号：US11594266B2

公开(公告)日：2023-02-28

申请号：US17195712

申请日：2021-03-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan Lin ,  Chao-Hung Wang

IPC: G11C7/00 ,  G11C7/22 ,  G06F3/06

Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD′.

公开(公告)号：US20180336946A1

公开(公告)日：2018-11-22

申请号：US15600851

申请日：2017-05-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan Lin ,  Chao-I Wu ,  Dai-Ying Lee

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0064 ,  G11C2013/0042 ,  G11C2013/0057

Abstract: A memory operating method and a memory operating device are provided. The memory operating method includes the following steps. A first stepping loop is performed. A second stepping loop is performed. In the first stepping loop, a first control voltage applied to a first control line is increased from a first initial value to a first final value which is larger than the first initial value, and a second control voltage applied to a second control line is fixed at a second initial value. In the second stepping loop, the first control voltage applied to the first control line is fixed at a fixing value, and the second control voltage applied to the second control line is increased from an intermediate value to a second final value which is larger than the second initial value.

公开(公告)号：US12260913B2

公开(公告)日：2025-03-25

申请号：US18166484

申请日：2023-02-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Yu-Hsuan Lin ,  Po-Hao Tseng

IPC: G11C5/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

Abstract: A hyperdimensional computing device includes a non-volatile memory cell array and a first operation circuit. The non-volatile memory cell array is coupled to a plurality of first word lines. The non-volatile memory cell array has a plurality of memory cell groups, a plurality of first memory cells of each of the memory cell groups are coupled to a same first word line of the first word lines, and the memory cell groups respectively store a plurality of data vectors. The first operation circuit receives at least one of the data vectors through bit lines and generates a bundled data vector according to the at least one of the data vectors.

公开(公告)号：US12198766B2

公开(公告)日：2025-01-14

申请号：US18172306

申请日：2023-02-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Yu-Hsuan Lin ,  Yu-Yu Lin ,  Hsiang-Lan Lung

IPC: G11C16/12 ,  G11C16/08 ,  G11C16/24

Abstract: An artificial neural network operation circuit and an in-memory computation device of the artificial neural network operation circuit are proposed. The in-memory computation device includes a memory cell array, a compensation memory cell string, and an operator. The memory cell array has a plurality of memory cells to store a plurality of weight values. The memory cell array has a plurality of word lines and a plurality of bit lines. Each compensation memory cell of the compensation memory cell string stores a unit weight value. The operator multiplies a signal on a compensation bit line by peak weight information of the weight values to generate a first signal and adds the first signal to each signal on the bit lines to obtain a plurality of computation results, respectively.

公开(公告)号：US11871588B2

公开(公告)日：2024-01-09

申请号：US17392365

申请日：2021-08-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Feng-Min Lee ,  Erh-Kun Lai ,  Dai-Ying Lee ,  Yu-Hsuan Lin ,  Po-Hao Tseng ,  Ming-Hsiu Lee

IPC: H10B63/00 ,  H10B61/00 ,  H10N50/01 ,  H10N70/00

CPC classification number: H10B63/845 ,  H10B61/22 ,  H10B63/34 ,  H10N50/01 ,  H10N70/066

Abstract: A memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

公开(公告)号：US11587623B2

公开(公告)日：2023-02-21

申请号：US17320336

申请日：2021-05-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Yu-Hsuan Lin ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: G11C16/26 ,  G11C16/04 ,  G11C5/06 ,  G11C15/04 ,  G11C16/30

Abstract: A content-address memory (CAM) and an operation method are provided. The content-address memory comprises: a plurality of first signal lines; a plurality of second signal lines; and a plurality of CAM memory cells coupled to the first signal lines and the second signal lines, wherein in data match, a plurality of input signals are input into the CAM memory cells via the first signal lines; the input signals are compared with contents stored in the CAM memory cells; and a match result is determined based on an electrical characteristic of the second signal lines.

公开(公告)号：US11557354B2

公开(公告)日：2023-01-17

申请号：US17166484

申请日：2021-02-03

Applicant: MACRONIX International Co., Ltd.

Inventor： Feng-Min Lee ,  Po-Hao Tseng ,  Yu-Hsuan Lin ,  Ming-Hsiu Lee

IPC: G11C16/30 ,  H01L29/788 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  H01L29/792 ,  H01L29/423 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11529 ,  G11C11/56 ,  H01L27/1157

Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.

公开(公告)号：US20220238151A1

公开(公告)日：2022-07-28

申请号：US17344555

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Yu-Hsuan Lin ,  Po-Hao Tseng ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: G11C11/4093 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/408 ,  G06F7/501 ,  G06F7/523

Abstract: An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.

公开(公告)号：US11138497B2

公开(公告)日：2021-10-05

申请号：US16224602

申请日：2018-12-18

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Hsuan Lin ,  Chao-Hung Wang ,  Ming-Hsiu Lee

IPC: G06N3/063 ,  G11C11/54 ,  G11C27/00 ,  G11C7/10

Abstract: An in-memory computing device includes a plurality of synaptic layers including a first type of synaptic layer and a second type of synaptic layer. The first type of synaptic layer comprises memory cells of a first type of memory cell and the second type of synaptic layer comprises memory cells of a second type, the first type of memory cell being different than the second type of memory cell. The first and second types of memory cells can be different types of memories, have different structures, different memory materials, and/or different read/write algorithms, any one of which can result in variations in the stability or accuracy of the data stored in the memory cells.