公开(公告)号：US12198757B2

公开(公告)日：2025-01-14

申请号：US17842989

申请日：2022-06-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: G11C11/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

Abstract: A memory device and a method for operating the same are provided. The memory device includes a plurality of resistive memory cells and a control circuitry electrically connected to the plurality of resistive memory cells. The control circuitry provides operation modes to operate the plurality of resistive memory cells. The operation modes include a first program operation and a refresh operation. The first program operation includes applying a first program bias voltage to a selected resistive memory cell of the plurality of resistive memory cells to establish a low-resistance state in the selected resistive memory cell. The first program operation establishes a first threshold voltage in the memory device. The refresh operation includes applying a refresh bias voltage to the selected resistive memory cell to refresh the selected resistive memory cell. An absolute value of the refresh bias voltage is greater than the first threshold voltage.

公开(公告)号：US12159672B2

公开(公告)日：2024-12-03

申请号：US18162728

申请日：2023-02-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Yu-Hsuan Lin ,  Tian-Cih Bo ,  Feng-Min Lee ,  Yu-Yu Lin

IPC: G11C16/04 ,  G11C15/04

Abstract: A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.

公开(公告)号：US12094564B2

公开(公告)日：2024-09-17

申请号：US17817701

申请日：2022-08-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yun-Yuan Wang ,  Cheng-Hsien Lu ,  Dai-Ying Lee ,  Ming-Hsiu Lee ,  Feng-Min Lee

IPC: G11C7/10

CPC classification number: G11C7/1063 ,  G11C7/1006 ,  G11C7/109

Abstract: The application provides a memory device and an operation method thereof. The memory device includes: a memory array, for processing model computation having a plurality of input values and a plurality of interact coefficients; and at least one calculation unit. In receiving the input values, a first part and a second part of the memory cells generate a first part and a second part of the common source currents, respectively. The first part of the memory cells is electrically isolated from the second part of the memory cells based on a diagonal of the memory array. The at least one calculation unit calculates a first part and a second part of a local field energy of the model computation based on the first part and the second part of the common source currents.

公开(公告)号：US12069857B2

公开(公告)日：2024-08-20

申请号：US17408535

申请日：2021-08-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan Lin ,  Feng-Min Lee ,  Po-Hao Tseng

IPC: H10B41/35 ,  H01L21/28 ,  H01L29/66

CPC classification number: H10B41/35 ,  H01L29/40114 ,  H01L29/66825

Abstract: The application discloses an integrated memory device, a manufacturing method and an operation method thereof. The integrated memory cell includes: a first memory cell; and an embedded second memory cell, serially coupled to the first memory cell, wherein the embedded second memory cell is formed on any one of a first side and a second side of the first memory cell.

公开(公告)号：US20230253032A1

公开(公告)日：2023-08-10

申请号：US18303194

申请日：2023-04-19

Applicant: MACRONIX International Co., Ltd.

Inventor： Yu-Hsuan Lin ,  Po-Hao Tseng ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: G11C11/4093 ,  G11C11/4091 ,  G06F7/523 ,  G11C11/408 ,  G06F7/501 ,  G11C11/4094

CPC classification number: G11C11/4093 ,  G11C11/4091 ,  G06F7/523 ,  G11C11/4085 ,  G06F7/501 ,  G11C11/4094

Abstract: An in-memory computation device and computation method are provided. The in-memory computation method includes: providing a memory cell block of a memory cell array to store a plurality of weight values, and providing a plurality of memory cells on the memory cell block to store a plurality of corresponding bits of each of the weight values; respectively transmitting a plurality of input signals to the plurality of bit lines through an input buffer; providing the plurality of memory cells to perform a multiplication operation of the plurality of input signals and the plurality of weight values to generate a plurality of first operation results respectively corresponding to a plurality of bit orders; and performing an addition operation on the plurality of first operation results to generate a second operation result according to the plurality of bit orders by a sense amplifier.

公开(公告)号：US11664070B2

公开(公告)日：2023-05-30

申请号：US17344555

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Yu-Hsuan Lin ,  Po-Hao Tseng ,  Feng-Min Lee ,  Ming-Hsiu Lee

IPC: G11C11/4093 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G06F7/523 ,  G06F7/501

CPC classification number: G11C11/4093 ,  G06F7/501 ,  G06F7/523 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094

Abstract: An in-memory computation device and computation method are provided. The in-memory computation device, including a memory cell array, an input buffer, and a sense amplifier, is provided. The memory cell array includes a memory cell block. The memory cell block corresponds to at least one word line, and stores multiple weight values. Memory cells on the memory cell block respectively store multiple bits of each weight value. The input buffer is coupled to multiple bit lines, and respectively transmits multiple input signals to the bit lines. The memory cell array performs a multiply-add operation on the input signals and the weight values to generate multiple first operation results corresponding to multiple bit orders. The sense amplifier adds the first operation results to generate a second operation result according to the bit orders corresponding to the first operation results.

公开(公告)号：US20230095392A1

公开(公告)日：2023-03-30

申请号：US18073366

申请日：2022-12-01

Applicant: MACRONIX International Co., Ltd.

Inventor： Feng-Min Lee ,  Po-Hao Tseng ,  Yu-Hsuan Lin ,  Ming-Hsiu Lee

IPC: G11C16/30 ,  H01L29/788 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  H01L29/792 ,  H01L29/423 ,  H01L27/11573 ,  H01L27/11524 ,  H01L27/11529 ,  G11C11/56 ,  H01L27/1157

Abstract: A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.

公开(公告)号：US11569445B2

公开(公告)日：2023-01-31

申请号：US17162803

申请日：2021-01-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee

IPC: H01L45/00

Abstract: Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming a bottom adhesion layer in a via formed in an insulating layer. Forming a bottom conductive plug in the bottom adhesion layer. Forming a top adhesion layer over the bottom adhesion layer and bottom conductive plug. Forming a top conductive plug in the top adhesion layer. Wherein the thickness of the bottom and top adhesion layers may be different from one another.

公开(公告)号：US10811602B2

公开(公告)日：2020-10-20

申请号：US15836446

申请日：2017-12-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Dai-Ying Lee ,  Feng-Min Lee

IPC: H01L45/00 ,  G11C13/00 ,  H01L21/768 ,  H01L27/24

Abstract: Memory devices based on tungsten oxide memory elements are described, along with methods for manufacturing such devices. A memory device includes a plug extending upwardly from a top surface of a substrate through a dielectric layer; a bottom electrode having tungsten on an outside surface, the bottom electrode extending upwardly from a top surface of the plug; an insulating material in contact with the tungsten on the outside surface of, and surrounding, the bottom electrode; a memory element on an upper surface of the bottom electrode, the memory element comprising a tungsten oxide compound and programmable to at least two resistance states; and a top electrode overlying and contacting the memory element. The plug has a first lateral dimension, and the bottom electrode has a lateral dimension parallel with the first lateral dimension of the plug that is less than the first lateral dimension.

公开(公告)号：US10460444B2

公开(公告)日：2019-10-29

申请号：US15922987

申请日：2018-03-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee

IPC: G06T7/11 ,  G06T1/60 ,  G06K9/62 ,  G06K9/46

Abstract: Disclosed is a memory device including plural bit lines, plural word lines and a control circuit. The bit lines are configured to receive pixel data of an image. Each word line includes plural factor units. The factor units of each word line are configured differently according to plural factors of a filter. When processing a first area of the image by the filter, the control circuit inputs the pixel data within the first area of the image to the bit lines, and enables one of the word lines for operation. When processing a second area of the image by the filter, the control circuit maintains the pixel data within the second area overlapping the first area on the bit lines, and inputs the pixel data within the second area which doesn't overlap the first area to the bit lines, and enables another one of the word lines for operation.