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    MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS
    32.
    发明申请
    MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20230066649A1

    公开(公告)日：2023-03-02

    申请号：US17450729

    申请日：2021-10-13

    Applicant: Micron Technology, Inc.

    Inventor： Erwin E. Yu ,  Surendranath C. Eruvuru ,  Yoshiaki Fukuzumi ,  Tomoko Ogura Iwasaki

    IPC: H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  G11C16/24 ,  G11C7/10 ,  B81B7/02

    Abstract: A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.

    MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS
    33.
    发明申请
    MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS 有权

    公开(公告)号：US20230039026A1

    公开(公告)日：2023-02-09

    申请号：US17396825

    申请日：2021-08-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

    Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

    Memory array structures and methods for determination of resistive characteristics of access lines
    35.
    发明授权
    Memory array structures and methods for determination of resistive characteristics of access lines 有权

    公开(公告)号：US11557341B2

    公开(公告)日：2023-01-17

    申请号：US17011018

    申请日：2020-09-03

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu ,  Paolo Tessariol ,  Tomoko Ogura Iwasaki

    IPC: G11C13/00

    Abstract: Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.

    MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM
    36.
    发明申请
    MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20220277795A1

    公开(公告)日：2022-09-01

    申请号：US17745852

    申请日：2022-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Kalyan Chakravarthy Kavalipurapu ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Hong-Yan Chen ,  Yunfei Xu

    IPC: G11C16/16 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08

    Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline.

    MANAGING PROGRAMMING CONVERGENCE ASSOCIATED WITH MEMORY CELLS OF A MEMORY SUB-SYSTEM
    37.
    发明申请
    MANAGING PROGRAMMING CONVERGENCE ASSOCIATED WITH MEMORY CELLS OF A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20220180952A1

    公开(公告)日：2022-06-09

    申请号：US17115357

    申请日：2020-12-08

    Applicant: Micron Technology, Inc.

    Inventor： Jun Xu ,  Violante Moschiano ,  Erwin E. Yu

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08

    Abstract: A first programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. In response to first programming pulse, causing a program verify operation to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sensing node is identified. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell.

    Managing sub-block erase operations in a memory sub-system
    38.
    发明授权
    Managing sub-block erase operations in a memory sub-system 有权

    公开(公告)号：US11335412B2

    公开(公告)日：2022-05-17

    申请号：US16991836

    申请日：2020-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Kalyan Chakravarthy Kavalipurapu ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Hong-Yan Chen ,  Yunfei Xu

    IPC: G11C16/16 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08

    Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval.

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