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    DRAIN SELECT GATE FORMATION METHODS AND APPARATUS
    32.
    发明申请
    DRAIN SELECT GATE FORMATION METHODS AND APPARATUS 有权
    排水选择门形成方法和装置

    公开(公告)号：US20160233225A1

    公开(公告)日：2016-08-11

    申请号：US14619243

    申请日：2015-02-11

    Applicant: Micron Technology, Inc.

    Inventor： Hongbin Zhu ,  Lijing Gou ,  Gordon Haller ,  Luan C. Tran

    IPC: H01L27/115

    CPC classification number: H01L27/11556 ,  H01L27/11582

    Abstract: Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.

    Abstract translation: 一些实施例包括沿着半导体材料的垂直沟道形成的一串电荷存储装置; 漏极选择栅极（SGD）晶体管的栅极区域，所述栅极区域至少部分地围绕所述垂直沟道; 在所述栅极区域中形成的介质阻挡层; 形成在所述栅极区域和所述电介质屏障之上的第一隔离层; 形成在垂直沟道上方的SGD晶体管的漏极区域; 以及形成在所述第一隔离层和所述漏极区之上的第二隔离层，其中所述第二隔离层包括与所述SGD晶体管的漏极区域电接触的导电接触。 公开了附加的装置和方法。

    MEMORY HAVING A CONTINUOUS CHANNEL
    33.
    发明申请
    MEMORY HAVING A CONTINUOUS CHANNEL 有权
    具有连续通道的记忆

    公开(公告)号：US20160099252A1

    公开(公告)日：2016-04-07

    申请号：US14831011

    申请日：2015-08-20

    Applicant: Micron Technology, Inc.

    Inventor： Luan C. Tran ,  Hongbin Zhu ,  John D. Hopkins ,  Yushi Hu

    IPC: H01L27/115

    CPC classification number: H01L27/11556 ,  H01L21/823412 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/11582 ,  H01L29/7827

    Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.

    Abstract translation: 本公开包括具有连续信道的存储器及其处理方法。 许多实施例包括形成具有串联连接在源选择栅极和漏极选择栅极之间的存储单元的垂直堆叠，其中形成垂直堆叠包括形成用于源选择栅极，存储器单元和漏极选择的连续沟道 栅极，并且去除用于漏极选择栅极的连续沟道的一部分，使得连续沟道对于漏极选择栅极比对于存储器单元和源选择栅极更薄。

    Method of making a semiconductor device
    34.
    发明授权
    Method of making a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US09305844B2

    公开(公告)日：2016-04-05

    申请号：US14626573

    申请日：2015-02-19

    Applicant: Micron Technology, Inc.

    Inventor： Hongbin Zhu ,  Gordon Haller ,  Paul D. Long

    IPC: H01L29/76 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/66 ,  H01L27/115

    CPC classification number: H01L21/823412 ,  H01L23/5226 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66787 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.

    Abstract translation: 一些实施例包括具有堆叠结构的半导体器件，该堆叠结构包括形成在衬底上的多个交替层的介电材料和多晶硅。 这样的半导体器件还可以包括至少一个具有高纵横比并且延伸到堆叠结构中的开口至与衬底相邻的水平，形成在邻近衬底的开口下部的第一多晶硅沟道，第二聚硅 - 硅沟道，以及设置在开口中的第一多晶硅沟道和第二多晶硅沟道之间的WSiX材料。 WSiX材料与衬底相邻，并且可以用作蚀刻着色层和导电触点，以在开口中接触第一多晶硅沟道和第二多晶硅沟道。 其他实施例包括制造半导体器件的方法。

    Memory Arrays
    35.
    发明申请
    Memory Arrays 有权
    记忆阵列

    公开(公告)号：US20150333143A1

    公开(公告)日：2015-11-19

    申请号：US14281569

    申请日：2014-05-19

    Applicant: Micron Technology, Inc.

    Inventor： John M. Meldrim ,  Yushi Hu ,  Rita J. Klein ,  John D. Hopkins ,  Hongbin Zhu ,  Gordon A. Haller ,  Luan C. Tran

    IPC: H01L29/49 ,  H01L21/28 ,  H01L27/115

    CPC classification number: H01L27/11582 ,  H01L21/28097 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4975

    Abstract: Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures.

    Abstract translation: 一些实施例包括具有交替的第一和第二电平的堆叠的存储器阵列。 通道材料柱延伸通过堆叠，并且垂直堆叠的存储器单元串沿着通道材料柱。 一个共同的来源在堆叠下，并且电耦合到通道材料柱。 普通源在金属硅化物上方具有导电保护材料，并且直接抵抗金属硅化物，导电保护材料是金属硅化物以外的组合物。 一些实施例包括制造集成结构的方法。

    Memory having a continuous channel
    37.
    发明授权
    Memory having a continuous channel 有权

    公开(公告)号：US11315941B2

    公开(公告)日：2022-04-26

    申请号：US16291453

    申请日：2019-03-04

    Applicant: Micron Technology, Inc.

    Inventor： Luan C. Tran ,  Hongbin Zhu ,  John D. Hopkins ,  Yushi Hu

    IPC: H01L27/11556 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/11582 ,  H01L29/78

    Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.

    Semiconductor devices and methods of fabrication
    38.
    发明授权
    Semiconductor devices and methods of fabrication 有权

    公开(公告)号：US11088168B2

    公开(公告)日：2021-08-10

    申请号：US16834291

    申请日：2020-03-30

    Applicant: Micron Technology, Inc.

    Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/66

    Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

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