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    Methods Of Forming An Array Of Cross Point Memory Cells
    31.
    发明申请
    Methods Of Forming An Array Of Cross Point Memory Cells 审中-公开

    公开(公告)号：US20180342671A1

    公开(公告)日：2018-11-29

    申请号：US16036238

    申请日：2018-07-16

    Applicant: Micron Technology, Inc.

    Inventor： Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L45/00 ,  G11C11/22 ,  H01L27/11507 ,  H01L27/24

    Abstract: A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross elevationally over the first lines and between the electrode pillars that are along the first lines. The electrode pillars and walls form spaced openings between the first lines. The openings are lined with programmable material of the memory cells being formed to less-than-fill the openings with the programmable material. Conductive upper electrode material is formed over the programmable material within remaining volume of the openings and spaced upper second lines are formed which cross the first lines elevationally over the conductive upper electrode material that is within the openings. A select device is between the lower electrode pillar and the underlying first line or is between the conductive upper electrode material and the overlying second line for the individual memory cells. Aspects of the invention include an array of cross point memory cells independent of method of manufacture.

    Methods Of Forming An Array Of Cross Point Memory Cells
    33.
    发明申请
    Methods Of Forming An Array Of Cross Point Memory Cells 审中-公开

    公开(公告)号：US20180090679A1

    公开(公告)日：2018-03-29

    申请号：US15827059

    申请日：2017-11-30

    Applicant: Micron Technology, Inc.

    Inventor： Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L45/00 ,  G11C11/22 ,  H01L27/11507 ,  H01L27/24

    CPC classification number: H01L45/065 ,  G11C11/221 ,  H01L27/11507 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/16

    Abstract: A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being formed along and elevationally over spaced lower first lines. Walls cross elevationally over the first lines and between the electrode pillars that are along the first lines. The electrode pillars and walls form spaced openings between the first lines. The openings are lined with programmable material of the memory cells being formed to less-than-fill the openings with the programmable material. Conductive upper electrode material is formed over the programmable material within remaining volume of the openings and spaced upper second lines are formed which cross the first lines elevationally over the conductive upper electrode material that is within the openings. A select device is between the lower electrode pillar and the underlying first line or is between the conductive upper electrode material and the overlying second line for the individual memory cells. Aspects of the invention include an array of cross point memory cells independent of method of manufacture.

    Memory arrays and methods of forming memory cells
    35.
    发明授权
    Memory arrays and methods of forming memory cells 有权

    公开(公告)号：US09893277B2

    公开(公告)日：2018-02-13

    申请号：US15003715

    申请日：2016-01-21

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Scott E. Sills ,  John K. Zahurak

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/085 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675

    Abstract: Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is patterned into a series of lines that cross the series of rails. A pattern of the series of lines is transferred into the bottom electrode contact material. At least a portion of the sacrificial material is subsequently replaced with top electrode material. Some embodiments include memory arrays that contain a second series of electrically conductive lines crossing a first series of electrically conductive lines. Memory cells are at locations where the electrically conductive lines of the second series overlap the electrically conductive lines of the first series. First and second memory cell materials are within the memory cell locations. The first memory cell material is configured as planar sheets and the second memory cell material is configured as upwardly-opening containers.

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