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公开(公告)号：US09704542B2
公开(公告)日：2017-07-11
申请号：US14857305
申请日：2015-09-17
Applicant: Micron Technology, Inc.
Inventor： Shigekazu Yamada
CPC classification number: G11C7/1006 , G11C7/062 , G11C16/04 , G11C16/08 , G11C29/02 , G11C29/025 , G11C2029/1202 , G11C2029/5006
Abstract: The present invention is a circuit and method for measuring leakage on the plurality of word lines in a memory device. In one embodiment, a memory device may include a leakage measurement circuit that is coupled to a plurality of word lines of the memory device. The leakage measurement circuit may be operable to generate a reference current and to determine whether a leakage current on one of the plurality of word lines is acceptable relative to the reference current. In another embodiment, a method may include determining whether leakage on one of a plurality of word lines of a memory device is allowable using a circuit in the memory device.
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公开(公告)号：US20160351274A1
公开(公告)日：2016-12-01
申请号：US15164956
申请日：2016-05-26
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan , Shigekazu Yamada
CPC classification number: G11C29/50 , G11C16/06 , G11C29/025 , G11C2029/5006
Abstract: A first switch is closed to initialize a circuit by charging a capacitance of the circuit. A second switch is closed to initialize an amplifier in unity-gain configuration. The amplifier is capacitively coupled to the circuit. The first switch and the second switch are then opened to detect a leakage current of the circuit by detecting a change in an output voltage of the amplifier.
Abstract translation: 关闭第一开关以通过对电路的电容进行充电来初始化电路。 闭合的第二个开关以单位增益配置初始化放大器。 放大器电容耦合到电路。 然后打开第一开关和第二开关，以通过检测放大器的输出电压的变化来检测电路的漏电流。
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33.发明授权公开(公告)号：US09064577B2
公开(公告)日：2015-06-23
申请号：US13707067
申请日：2012-12-06
Applicant: Micron Technology, Inc.
Inventor： Han Zhao , Akira Goda , Krishna K. Parat , Aurelio Giancarlo Mauri , Haitao Liu , Toru Tanzawa , Shigekazu Yamada , Koji Sakui
CPC classification number: G11C16/3459 , G11C8/08 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/32 , G11C16/3445 , G11C2213/71
Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body.
Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。
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公开(公告)号：US08947946B2
公开(公告)日：2015-02-03
申请号：US14084408
申请日：2013-11-19
Applicant: Micron Technology, Inc.
Inventor： Shigekazu Yamada
CPC classification number: G11C7/06 , G11C16/00 , G11C16/0483 , G11C29/025 , G11C29/50008 , G11C2029/1202 , G11C2029/5006
Abstract: Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a supply voltage. The boosted voltage may be generated by charge pump circuitry. Examples of leakage measurement systems described herein may be included in memory devices.
Abstract translation: 所描述的示例包括泄漏测量系统和用于测量升压电压的字线与电源电压下的字线之间的漏电流的方法。 升压电压可能由电荷泵电路产生。 这里描述的泄漏测量系统的示例可以包括在存储器设备中。
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35.发明申请公开(公告)号：US20140133249A1
公开(公告)日：2014-05-15
申请号：US14160158
申请日：2014-01-21
Applicant: Micron Technology, Inc.
Inventor： Shigekazu Yamada
IPC: G11C29/02
CPC classification number: G11C29/025 , G11C8/08 , G11C2029/1202 , G11C2029/5006
Abstract: Methods, apparatuses, and integrated circuits for measuring leakage current are disclosed. In one such example method, a word line is charged to a first voltage, and a measurement node is charged to a second voltage, the second voltage being less than the first voltage. The measurement node is proportionally coupled to the word line. A voltage on the measurement node is compared with a reference voltage. A signal is generated, the signal being indicative of the comparison. Whether a leakage current of the word line is acceptable or not can be determined based on the signal.
Abstract translation: 公开了用于测量泄漏电流的方法，装置和集成电路。 在一个这样的示例方法中，字线被充电到第一电压，并且测量节点被充电到第二电压，第二电压小于第一电压。 测量节点按比例耦合到字线。 将测量节点上的电压与参考电压进行比较。 产生信号，该信号表示比较。 可以基于该信号来确定字线的泄漏电流是否可接受。
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Patent Agency Ranking
公开(公告)号：US20240233825A9
公开(公告)日：2024-07-11
申请号：US18489454
申请日：2023-10-18
Applicant: Micron Technology, Inc.
Inventor： Federica Paolini , Violante Moschiano , Marco Domenico Tiburzi , Leo Raimondo , Filippo Bruno , Shigekazu Yamada
CPC classification number: G11C16/08 , G11C16/0483 , G11C16/26 , G11C16/30
Abstract: A system includes a memory device having one or more planes and a first set of voltage regulators coupled to each plane of the one or more planes, where the first set of voltage regulators is shared by the one or more planes. The system includes a second set of voltage regulators coupled to a plane of the one or more planes configured to supply a respective voltage to one or more conductive lines responsive to a memory access operation request. The system includes a switch, at the plane of the one or more planes, coupled with a first voltage regulator of the first set of voltage regulators, a second voltage regulator of the second set of voltage regulators, and a first conductive line, the switch configured to selectively couple the second voltage regulator of the second set of voltage regulators to the first conductive line.
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公开(公告)号：US20240135994A1
公开(公告)日：2024-04-25
申请号：US18489454
申请日：2023-10-17
Applicant: Micron Technology, Inc.
Inventor： Federica Paolini , Violante Moschiano , Marco Domenico Tiburzi , Leo Raimondo , Filippo Bruno , Shigekazu Yamada
CPC classification number: G11C16/08 , G11C16/0483 , G11C16/26 , G11C16/30
Abstract: A system includes a memory device having one or more planes and a first set of voltage regulators coupled to each plane of the one or more planes, where the first set of voltage regulators is shared by the one or more planes. The system includes a second set of voltage regulators coupled to a plane of the one or more planes configured to supply a respective voltage to one or more conductive lines responsive to a memory access operation request. The system includes a switch, at the plane of the one or more planes, coupled with a first voltage regulator of the first set of voltage regulators, a second voltage regulator of the second set of voltage regulators, and a first conductive line, the switch configured to selectively couple the second voltage regulator of the second set of voltage regulators to the first conductive line.
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公开(公告)号：US11355206B2
公开(公告)日：2022-06-07
申请号：US17200317
申请日：2021-03-12
Applicant: Micron Technology, Inc.
Inventor： Shigekazu Yamada
Abstract: Discussed herein are systems and methods for compensating degradation of a transistor in a high-voltage (HV) shifter configured to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises a group of memory cells, and a HV shifter circuit including a signal transfer circuit and a compensator circuit. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The compensator circuit can provide a control signal to the signal transfer circuit by coupling a support voltage higher than a supply voltage (Vcc) to the signal transfer circuit for a specified time period to compensate for degradation of the P-channel transistor. The transferred high voltage is used to charge the access line to selectively read, program, or erase memory cells.
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公开(公告)号：US11354067B2
公开(公告)日：2022-06-07
申请号：US16947525
申请日：2020-08-05
Applicant: Micron Technology, Inc.
Inventor： Kalyan Chakravarthy C. Kavalipurapu , Chang H. Siau , Shigekazu Yamada
Abstract: A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.
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公开(公告)号：US20210202016A1
公开(公告)日：2021-07-01
申请号：US17200317
申请日：2021-03-12
Applicant: Micron Technology, Inc.
Inventor： Shigekazu Yamada
Abstract: Discussed herein are systems and methods for compensating degradation of a transistor in a high-voltage (HV) shifter configured to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises a group of memory cells, and a HV shifter circuit including a signal transfer circuit and a compensator circuit. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The compensator circuit can provide a control signal to the signal transfer circuit by coupling a support voltage higher than a supply voltage (Vcc) to the signal transfer circuit for a specified time period to compensate for degradation of the P-channel transistor. The transferred high voltage is used to charge the access line to selectively read, program, or erase memory cells.
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