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    Corrupted storage portion recovery in a memory device
    31.
    发明授权
    Corrupted storage portion recovery in a memory device 有权

    公开(公告)号：US12056046B2

    公开(公告)日：2024-08-06

    申请号：US17136819

    申请日：2020-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Lalla Fatima Drissi ,  Giuseppe D'Eliseo ,  Paolo Papa ,  Massimo Iaculo ,  Carminantonio Manganelli

    IPC: G06F12/02 ,  G06F3/06

    CPC classification number: G06F12/0253 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/0679

    Abstract: Devices and techniques for corrupted storage portion recovery in a memory device are described herein. A failure event can be detected during a garbage collection operation on a collection of storage portions (e.g., pages) in a memory array. Here, members of the collection of storage portions are being moved from a former physical location to a new physical location by the garbage collection operation. A reference to a former physical location of a possibly corrupt storage portion in the collection of storage portions can be retrieved in response to the failure event. Here, the possibly corrupt storage portion has already been written to a new physical location as part of the garbage collection operation. The possibly corrupt storage portion can then be rewritten at the new physical location using data from the former physical location.

    DATA BLOCK REFRESH DURING READ ACCESS
    32.
    发明公开
    DATA BLOCK REFRESH DURING READ ACCESS 审中-公开

    公开(公告)号：US20240168654A1

    公开(公告)日：2024-05-23

    申请号：US18504985

    申请日：2023-11-08

    Applicant: Micron Technology, Inc.

    Inventor： Luca Porzio ,  Ting Luo ,  Ciro Feliciano ,  Giuseppe D'Eliseo

    IPC: G06F3/06 ,  G06F12/1009

    CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/1009

    Abstract: Methods, systems, and devices for data block refresh during read access are described. In some instances, when an access command (e.g., a read command) is received, a memory system may determine if the associated block is a PSA block. If the block is PSA block, its data may be provided to a host system to satisfy the read command and the block may either be refreshed or may be designated to be refreshed. For example, the block may be refreshed by copying its data to a write cache and writing the data from the cache to a new block. In other instances, an LBA of the block may be stored (e.g., designated) and the LBA may be refreshed when the memory system is idle.

    Cache read context switching in a memory sub-system
    33.
    发明授权
    Cache read context switching in a memory sub-system 有权

    公开(公告)号：US11886346B2

    公开(公告)日：2024-01-30

    申请号：US17302067

    申请日：2021-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe D'Eliseo ,  Anna Scalesse ,  Umberto Siciliani ,  Carminantonio Manganelli

    IPC: G06F12/00 ,  G06F12/0844 ,  G06F3/06

    CPC classification number: G06F12/0844 ,  G06F3/0659 ,  G06F2212/1021

    Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a plurality of cache read commands requesting first data from the memory array spread across the plurality of memory planes and receives, from the requestor, a cache read context switch command and a snap read command requesting second data from one of the plurality of memory planes of the memory array. Responsive to receiving the cache read context switch command, the control logic suspends processing of the plurality of cache read commands and processes the snap read command to read the second data from the memory array and return the second data to the requestor.

    Dynamic P2L asynchronous power loss mitigation
    35.
    发明授权
    Dynamic P2L asynchronous power loss mitigation 有权

    公开(公告)号：US11675411B2

    公开(公告)日：2023-06-13

    申请号：US17470506

    申请日：2021-09-09

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe D'Eliseo ,  Xiangang Luo ,  Ting Luo ,  Jianmin Huang

    IPC: G06F1/3206 ,  G06F12/06 ,  G06F12/02 ,  G06F1/3296

    CPC classification number: G06F1/3206 ,  G06F1/3296 ,  G06F12/0246 ,  G06F12/06

    Abstract: Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area and an address of the first P2L data structure can be stored in the second P2L data structure.

    CACHE READ CONTEXT SWITCHING IN A MEMORY SUB-SYSTEM
    37.
    发明申请
    CACHE READ CONTEXT SWITCHING IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20220342823A1

    公开(公告)日：2022-10-27

    申请号：US17302067

    申请日：2021-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe D'Eliseo ,  Anna Scalesse ,  Umberto Siciliani ,  Carminantonio Manganelli

    IPC: G06F12/0844

    Abstract: A memory device includes a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a plurality of cache read commands requesting first data from the memory array spread across the plurality of memory planes and receives, from the requestor, a cache read context switch command and a snap read command requesting second data from one of the plurality of memory planes of the memory array. Responsive to receiving the cache read context switch command, the control logic suspends processing of the plurality of cache read commands and processes the snap read command to read the second data from the memory array and return the second data to the requestor.

    Scheme to improve efficiency of garbage collection in cached flash translation layer
    38.
    发明授权
    Scheme to improve efficiency of garbage collection in cached flash translation layer 有权

    公开(公告)号：US11455245B2

    公开(公告)日：2022-09-27

    申请号：US16076288

    申请日：2017-12-11

    Applicant: Micron Technology, Inc.

    Inventor： Xinghui Duan ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Giuseppe Ferrari ,  Eric Kwok Fung Yuen ,  Massimo Iaculo

    IPC: G06F12/02 ,  G06F12/1009

    Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which storage in the memory device is managed. An allocation can include conducting a garbage collection procedure to free up one or more blocks. In various embodiments, execution of a garbage collection procedure can be based on operation of two tables with respect to a logical to physical mapping table split into logical to physical mapping table regions saved in the memory device. The first table can maintain counts of valid pages in blocks for a logical to physical mapping table region. The second table can include bits to identify logical to physical mapping table regions involved in the garbage collection procedure based on the entries in the first table. Search of the second table can determine logical to physical mapping table regions involved in the garbage collection. Additional apparatus, systems, and methods are disclosed.

    Reading Sequential Data from Memory Using a Pivot Table
    39.
    发明申请
    Reading Sequential Data from Memory Using a Pivot Table 有权

    公开(公告)号：US20220027284A1

    公开(公告)日：2022-01-27

    申请号：US17494740

    申请日：2021-10-05

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe D'Eliseo ,  Carminantonio Manganelli ,  Paolo Papa ,  Yoav Weinberg ,  Giuseppe Ferrari ,  Massimo Iaculo ,  Lalla Fatima Drissi

    IPC: G06F12/1009

    Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.

    Controlling NAND operation latency
    40.
    发明授权
    Controlling NAND operation latency 有权

    公开(公告)号：US11169917B2

    公开(公告)日：2021-11-09

    申请号：US16742215

    申请日：2020-01-14

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe D'Eliseo ,  Luigi Esposito ,  Xinghui Duan ,  Lucia Santojanni ,  Massimo Iaculo

    IPC: G06F12/02 ,  G11C16/10

    Abstract: Devices and techniques for controlling NAND operation latency are described herein. A controlled can receive a write request. The controller can then calculate a number of garbage collection operations to perform on a physical block that is closed. Here, the calculation includes adding a logical-to-physical (L2P) region search ratio to a cadence calculation for garbage collection. Garbage collection operations can be performed on the physical block in accordance with the calculated number of garbage collection operations to perform. Then, the controller can perform the write request in response to completing the calculated number of garbage collection operations.

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