公开(公告)号：US11778823B2

公开(公告)日：2023-10-03

申请号：US17125407

申请日：2020-12-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Guan-Ru Lee

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: The present disclosure provides a three-dimensional memory device and a method for manufacturing the same. The three-dimensional memory device includes a plurality of tiles, and each tiles includes a plurality of blocks, and each blocks includes a gate stacked structure, a conductive layer, first ring-shaped channel pillars, source/drain pillars, and charge storage structures. The gate stacked structure is disposed on the substrate and includes gate layers electrically insulated from each other. The conductive layer is disposed between the substrate and the gate stacked structure. The first ring-shaped channel pillars are disposed on the substrate and located in the gate stacked structure. The source/drain pillars are disposed on the substrate, and each of the first ring-shaped channel pillars are configured with two source/drain pillars disposed therein. Each of the charge storage structures is disposed between the corresponding gate layer and the corresponding first ring-shaped channel pillar. The conductive layer in one of the tiles is isolated from the conductive layers in the other tiles.

公开(公告)号：US20230225126A1

公开(公告)日：2023-07-13

申请号：US17575418

申请日：2022-01-13

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Chia-Jung Chiu ,  Teng-Hao Yeh ,  Guan-Ru Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: A three-dimensional AND flash memory device includes a gate stack structure, a charge storage structure, a first conductive pillar and a second conductive pillar, an insulating pillar, and a channel pillar. The gate stack structure includes gate layers and insulating layers stacked alternately with each other. The first and second conductive pillars extend through the gate stack structure. The channel pillar extends through the gate stack structure. The charge storage structure is disposed between the gate stack structure and the channel pillar. The channel pillar includes: a first part and a second part connected each other. The first part is located between the charge storage structure and the insulating pillar. The second part includes a first region electrically connected to the first conductive pillar, and a second region electrically connected to the second conductive pillar. A curvature of the first part is smaller than a curvature of the second part.

公开(公告)号：US20220157848A1

公开(公告)日：2022-05-19

申请号：US17185275

申请日：2021-02-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Guan-Ru Lee

IPC: H01L27/11582 ,  H01L27/11565

Abstract: Provided is a memory device including a substrate, a stack structure, a polysilicon layer, a vertical channel structure, and a charge storage structure. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The polysilicon layer is disposed between the substrate and the stack structure. The vertical channel structure penetrates through the stack structure and the polysilicon layer. The charge storage structure is at least disposed between the vertical channel structure and the plurality of conductive layers.

公开(公告)号：US11195847B2

公开(公告)日：2021-12-07

申请号：US16412596

申请日：2019-05-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Min-Feng Hung ,  Chia-Jung Chiu ,  Guan-Ru Lee

IPC: H01L27/11582 ,  H01L21/762 ,  H01L29/417

Abstract: A memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.

公开(公告)号：US09754790B2

公开(公告)日：2017-09-05

申请号：US14711874

申请日：2015-05-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru Lee

IPC: H01L29/76 ,  H01L21/283 ,  H01L29/04 ,  H01L29/16 ,  H01L27/11582

CPC classification number: H01L21/283 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16

Abstract: A memory device comprises a patterned multi-layers stacking structure, a semiconductor capping layer, a memory layer and a channel layer. The patterned multi-layers stacking structure is formed on a substrate and has at least one trench used to define a plurality of ridge-shaped stacks comprising at least one conductive strip in the patterned multi-layers stacking structure. The semiconductor capping layer covers on the ridge-shaped stacks. The memory layer covers on sidewalls of the trench. The channel layer covers on the memory layer, the semiconductor capping layer and a bottom of the trench, wherein the channel layer is directly in contact with the semiconductor capping layer.

公开(公告)号：US20150357342A1

公开(公告)日：2015-12-10

申请号：US14297346

申请日：2014-06-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru Lee

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/28282

Abstract: A memory device includes a plurality of stacks of conductive strips alternating with insulating strips. At least one of the insulating strips includes an insulating material with a dielectric constant equal to or lower than 3.6. A plurality of structures of a conductive material is arranged orthogonally over the stacks. Memory elements are disposed in interface regions at cross-points between side surfaces of the stacks and structures. The insulating strips can have equivalent oxide thicknesses EOT substantially greater than their respective physical thicknesses. The EOT can be at least 10% greater than the respective physical thicknesses. The at least one of the insulating strips can consist essentially of the insulating material with a dielectric constant equal to or lower than 3.6.

Abstract translation: 存储器件包括与绝缘条交替的多个导电条的叠层。 绝缘条中的至少一个包括介电常数等于或小于3.6的绝缘材料。 导电材料的多个结构被正交布置在堆叠上。 存储元件设置在堆叠和结构的侧表面之间的交叉点处的界面区域中。 绝缘条可以具有基本上大于其相应物理厚度的等效氧化物厚度EOT。 EOT可以比相应的物理厚度大至少10％。 绝缘条中的至少一个绝缘条可基本由绝缘材料组成，介电常数等于或小于3.6。

公开(公告)号：US09190467B2

公开(公告)日：2015-11-17

申请号：US14149873

申请日：2014-01-08

Applicant: Macronix International Co., Ltd.

Inventor： Erh-Kun Lai ,  Guan-Ru Lee ,  An-Chyi Wei ,  Hang-Ting Lue

IPC: H01L29/06 ,  H01L27/115 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/0603 ,  H01L27/11578 ,  H01L29/401 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7843

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked strip structure, and a tensile material strip. The stacked strip structure is formed vertically on the substrate, the stacked strip structure having compressive stress. The stacked strip structure comprises a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. The tensile material strip is formed on the stacked strip structure, the tensile material strip having tensile stress.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括基板，堆叠带状结构和拉伸材料带。 堆叠的带状结构垂直地形成在基板上，堆叠的带状结构具有压应力。 堆叠的带状结构包括多个导电条和多个绝缘条，并且导电条和绝缘条是交错的。 拉伸材料带形成在堆叠的带状结构上，拉伸材料带具有拉伸应力。

公开(公告)号：US09171862B2

公开(公告)日：2015-10-27

申请号：US14163815

申请日：2014-01-24

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Ru Lee

IPC: H01L27/115 ,  H01L21/3105 ,  H01L21/02 ,  H01L49/02 ,  H01L27/108

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31053 ,  H01L27/10852 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L28/91

Abstract: A method of forming a three-dimensional memory is provided. A stacked structure including semiconductor layers and insulating layers arranged alternately is formed on a substrate. The stacked structure is patterned to form a mesh structure having first strips extending in a first direction and second strips extending in a second direction. The first strips and the second strips intersect with each other. The mesh structure has first holes. A dielectric layer is formed in each first hole. At least a portion of the first strips of the mesh structure is removed to form second holes and bit line stacked structures separated from each other. A charge storage layer is formed on sidewall and bottom of each second hole. A gate pillar extending in a third direction is formed on each charge storage layer in the second hole. Word lines extending in the first direction are formed on the gate pillars.

Abstract translation: 提供了形成三维存储器的方法。 在基板上形成包括交替布置的半导体层和绝缘层的堆叠结构。 将堆叠的结构图案化以形成具有沿第一方向延伸的第一条带和沿第二方向延伸的第二条带的第二条带的网格结构。 第一条和第二条彼此相交。 网状结构具有第一孔。 在每个第一孔中形成介电层。 去除网状结构的第一条带的至少一部分以形成彼此分离的第二孔和位线堆叠结构。 在每个第二孔的侧壁和底部上形成电荷存储层。 在第二孔中的每个电荷存储层上形成沿第三方向延伸的栅极柱。 在门柱上形成沿第一方向延伸的字线。

公开(公告)号：US20150214241A1

公开(公告)日：2015-07-30

申请号：US14163815

申请日：2014-01-24

Applicant: MACRONIX International Co., Ltd.

Inventor： Guan-Ru Lee

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31053 ,  H01L27/10852 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L28/91

Abstract: A method of forming a three-dimensional memory is provided. A stacked structure including semiconductor layers and insulating layers arranged alternately is formed on a substrate. The stacked structure is patterned to form a mesh structure having first strips extending in a first direction and second strips extending in a second direction. The first strips and the second strips intersect with each other. The mesh structure has first holes. A dielectric layer is formed in each first hole. At least a portion of the first strips of the mesh structure is removed to form second holes and bit line stacked structures separated from each other. A charge storage layer is formed on sidewall and bottom of each second hole. A gate pillar extending in a third direction is formed on each charge storage layer in the second hole. Word lines extending in the first direction are formed on the gate pillars.

Abstract translation: 提供了形成三维存储器的方法。 在基板上形成包括交替布置的半导体层和绝缘层的堆叠结构。 将堆叠的结构图案化以形成具有沿第一方向延伸的第一条带和沿第二方向延伸的第二条带的第二条带的网格结构。 第一条和第二条彼此相交。 网状结构具有第一孔。 在每个第一孔中形成介电层。 去除网状结构的第一条带的至少一部分以形成彼此分离的第二孔和位线堆叠结构。 在每个第二孔的侧壁和底部上形成电荷存储层。 在第二孔中的每个电荷存储层上形成沿第三方向延伸的栅极柱。 在门柱上形成沿第一方向延伸的字线。

公开(公告)号：US20150194481A1

公开(公告)日：2015-07-09

申请号：US14149873

申请日：2014-01-08

Applicant: Macronix International Co., Ltd.

Inventor： Erh-Kun Lai ,  Guan-Ru Lee ,  An-Chyi Wei ,  Hang-Ting Lue

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/0603 ,  H01L27/11578 ,  H01L29/401 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7843

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked strip structure, and a tensile material strip. The stacked strip structure is formed vertically on the substrate, the stacked strip structure having compressive stress. The stacked strip structure comprises a plurality of conductive strips and a plurality of insulating strips, and the conductive strips and the insulating strips are interlaced. The tensile material strip is formed on the stacked strip structure, the tensile material strip having tensile stress.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括基板，堆叠带状结构和拉伸材料带。 堆叠的带状结构垂直地形成在基板上，堆叠的带状结构具有压应力。 堆叠的带状结构包括多个导电条和多个绝缘条，并且导电条和绝缘条是交错的。 拉伸材料带形成在堆叠的带状结构上，拉伸材料带具有拉伸应力。