公开(公告)号：US11443797B2

公开(公告)日：2022-09-13

申请号：US16798166

申请日：2020-02-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Shu-Yin Ho ,  Hsiang-Pang Li ,  Yao-Wen Kang ,  Chun-Feng Wu ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C11/54 ,  G11C11/4091 ,  G06N3/06 ,  G06N3/08 ,  G06F7/544 ,  G11C11/408 ,  G11C11/4094

Abstract: A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

公开(公告)号：US11354123B2

公开(公告)日：2022-06-07

申请号：US17026347

申请日：2020-09-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Han-Wen Hu ,  Yueh-Han Wu ,  Tse-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F7/544 ,  G06F9/345 ,  G06F9/30

Abstract: A computing in memory method for a memory device is provided. The computing in memory method includes: based on a stride parameter, unfolding a kernel into a plurality of sub-kernels and a plurality of complement sub-kernels; based on the sub-kernels and the complement sub-kernels, writing a plurality of weights into a plurality of target memory cells of a memory array of the memory device; inputting an input data into a selected word line of the memory array; performing a stride operation in the memory array; temporarily storing a plurality of partial sums; and summing the stored partial sums into a stride operation result when all operation cycles are completed.

公开(公告)号：US20210326114A1

公开(公告)日：2021-10-21

申请号：US17217482

申请日：2021-03-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Wei-Chen Wang ,  Chien-Chung Ho ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F7/544 ,  G06N3/04 ,  G06N3/08 ,  G06F7/483 ,  G11C13/00

Abstract: An in-memory computing method and apparatus, adapted for a processor to perform MAC operations on a memory, are provided. In the method, a format of binary data of weights is transformed from a floating-point format into a quantized format by truncating at least a portion of fraction bits of the binary data and calculating complements of remaining bits, and programming the transformed binary data into cells of the memory. A tuning procedure is performed by iteratively inputting binary data of input signals into the memory, integrating outputs of the memory, and adjusting the weights programmed to the cells based on the integrated outputs. The binary data of the weights is reshaped based on a probability of reducing bits with a value of one in the binary data of each weight. The tuning procedure is repeated until an end condition is met.

公开(公告)号：US20200312405A1

公开(公告)日：2020-10-01

申请号：US16798166

申请日：2020-02-21

Applicant: MACRONIX International Co., Ltd.

Inventor： SHU-YIN HO ,  Hsiang-Pang Li ,  Yao-Wen Kang ,  Chun-Feng Wu ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C11/54 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G06N3/06 ,  G06N3/08 ,  G06F7/544

Abstract: A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

公开(公告)号：US20190050156A1

公开(公告)日：2019-02-14

申请号：US15672430

申请日：2017-08-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06 ,  G06F12/02 ,  G11C7/04

Abstract: Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.

公开(公告)号：US10120605B2

公开(公告)日：2018-11-06

申请号：US15093841

申请日：2016-04-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Yu-Ming Chang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56

Abstract: A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to allocate the data; when the data is cold data, according to a cold data allocating order, searching at least one second empty sub-block from the physical memory block to allocate the data.

公开(公告)号：US09740602B2

公开(公告)日：2017-08-22

申请号：US14805498

申请日：2015-07-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F12/00 ,  G11C11/56 ,  G11C16/10 ,  G11C16/04

CPC classification number: G06F12/00 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7209 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page.

公开(公告)号：US09501396B2

公开(公告)日：2016-11-22

申请号：US13969462

申请日：2013-08-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Cheng-Yuan Wang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Pi-Cheng Hsiu ,  Tei-Wei Kuo

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/0238 ,  G06F12/0246 ,  G06F12/109 ,  G06F2212/1032 ,  G06F2212/7204 ,  G06F2212/7211

Abstract: A method for managing utilization of a memory including a physical address space comprises mapping logical addresses of data objects to locations within the physical address space, and defining a plurality of address segments in the space as an active window. The method comprises allowing writes of data objects having logical addresses mapped to locations within the plurality of address segments in the active window. The method comprises, upon detection of a request to write a data object having a logical address mapped to a location outside the active window, updating the mapping so that the logical address maps to a selected location within the active window, and then allowing the write to the selected location. The method comprises maintaining access data indicating utilization of the plurality of address segments in the active window, and adding and removing address segments from the active window in response to the access data.

Abstract translation: 一种用于管理包括物理地址空间的存储器的利用的方法包括将数据对象的逻辑地址映射到物理地址空间内的位置，以及将空间中的多个地址段定义为活动窗口。 该方法包括允许将具有映射到活动窗口中的多个地址段内的位置的逻辑地址的数据对象的写入。 该方法包括在检测到写入具有映射到活动窗口之外的位置的逻辑地址的数据对象的请求时，更新映射，使得逻辑地址映射到活动窗口内的选定位置，然后允许写入 到所选位置。 该方法包括维护指示在活动窗口中多个地址段的利用的访问数据，以及响应于访问数据从活动窗口添加和移除地址段。

公开(公告)号：US20150178010A1

公开(公告)日：2015-06-25

申请号：US14523006

申请日：2014-10-24

Applicant: Macronix International Co., Ltd.

Inventor： Ping-Chun Chang ,  Yuan-Hao Chang ,  Hung-Sheng Chang ,  Tei-Wei Kuo ,  Hsiang-Pang Li

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0679 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0292 ,  G06F2212/1024 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/7201

Abstract: A method is provided for managing a memory device including a plurality of physical memory segments. A logical memory space is classified into a plurality of classifications based on usage specifications. The plurality of physical memory segments is allocated to corresponding logical addresses based on the plurality of classifications, and on usage statistics of the physical memory segments. A data structure is maintained recording translation between logical addresses in the logical memory space and physical addresses of the physical memory segments. The plurality of classifications includes a first classification and a second classification having different usage statistic requirements than the first classification. Logical addresses having the second classification can be redirected to physical segments allocated to logical addresses having the first classification, and the data structure can be updated to record redirected logical addresses. A free command can release a physical memory segment allocated for main memory use.

Abstract translation: 提供了一种用于管理包括多个物理存储器段的存储器件的方法。 逻辑存储器空间根据使用规范被分类为多个分类。 基于多个分类，以及物理存储器段的使用统计，将多个物理存储器段分配给相应的逻辑地址。 数据结构保持在逻辑存储器空间中的逻辑地址和物理存储器段的物理地址之间进行记录转换。 多个分类包括与第一分类不同的使用统计要求的第一分类和第二分类。 具有第二分类的逻辑地址可以被重定向到分配给具有第一分类的逻辑地址的物理段，并且可以更新数据结构以记录重定向的逻辑地址。 免费命令可以释放分配给主内存使用的物理内存段。

公开(公告)号：US20140307505A1

公开(公告)日：2014-10-16

申请号：US14060296

申请日：2013-10-22

Applicant: Macronix International Co., Ltd

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsing-Chen Lu ,  Hsiang-Pang Li ,  Cheng-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C16/34

CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3427

Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.

Abstract translation: 描述了支持减少非易失性存储器的程序干扰的技术。 三/二维NAND阵列包括被分成多个页组的多页。 允许访问在三维NAND阵列的擦除块中的多个寻呼组的第一页组内的存储单元，同时访问最小化到擦除块中的多个页组的第二页组内的存储单元 的三/二维NAND阵列。 同一页组中的页面在三维/二维NAND阵列中彼此物理上不相邻。