公开(公告)号：US4937792A

公开(公告)日：1990-06-26

申请号：US327272

申请日：1989-03-22

申请人： Azuma Suzuki ,  Masataka Matsui

发明人： Azuma Suzuki ,  Masataka Matsui

IPC分类号： G11C11/417 ,  G06F1/32 ,  G11C7/22 ,  G11C8/18 ,  G11C11/407 ,  G11C11/419

CPC分类号： G06F1/32 ,  G11C11/419 ,  G11C7/22 ,  G11C8/18

摘要： A static random access memory device is comprised of a write mode detector for detecting a signal state transition of a write enable signal changing to an active state, an input data transition detector for detecting a transition of the input data supplied from exterior, during a contamination of the active state of the write enable signal, a power down timer for generating a pulse signal with a predetermined pulse width in response to either of the detecting signals outputted from the write mode detector and input data transition detector, a gate circuit for permitting the output data from a row decoder to be transferred to memory cells during a period that the power down timer generates a pulse signal, and for inhibiting that data transfer during a period that the power down timer rests, and a write circuit control circuit allowing a write circuit to supply write data to the bit line pair during a period that the power down timer generates a pulse signal, and prohibiting that write data transfer during a period that the power timer rests.

公开(公告)号：US4874639A

公开(公告)日：1989-10-17

申请号：US100767

申请日：1987-09-24

申请人： Masataka Matsui ,  Toshiaki Aono ,  Yoshio Tanimoto ,  Tadamitsu Nakahama ,  Takakazu Yamane

发明人： Masataka Matsui ,  Toshiaki Aono ,  Yoshio Tanimoto ,  Tadamitsu Nakahama ,  Takakazu Yamane

IPC分类号： B05B13/02 ,  B05D1/00 ,  B05D3/02

CPC分类号： B05D3/0272 ,  B05B13/0221 ,  B05D1/002 ,  B05B13/0452

摘要： The coating method contains a spraying step in which a paint is sprayed at least on a coating substrate extending in an upward and downward direction to a film thickness thicker than causing sags of the sprayed paint. The coating substrate on which the paint is sprayed is rotated about the horizontal axis while the sprayed paint is dried until it does not sag any more.The coating apparatus includes a carriage conveying the coating substrate arranged to run along the conveying direction, and the carriage is provided with a supporting base for supporting the coating substrate rotatively about the horizontal axis. One embodiment for rotating the substrate supported by the supporting base is a spring that is disposed on the carriage to rotate the substrate by means of a restoring force produced by the spring. On the passage for conveying the carriage is disposed a force storing mechanism for storing the restoring force in the spring that released the restoring force.Another embodiment therefor is a combination of a chain disposed along the conveying passage for the carriage with a sprocket disposed on the carriage. The sprocket is engageable with the chain and operatively coupled to the coating substrate. By disposing the chain in a fixed manner, on the one hand, the substrate is caused to rotate as the carriage is being conveyed. By dividing the chain, on the other, the substrate is caused to rotate while the conveyance of the carriage is suspended.

公开(公告)号：US6011713A

公开(公告)日：2000-01-04

申请号：US995769

申请日：1997-12-22

申请人： Fumiyuki Yamane ,  Tadahiro Kuroda ,  Toshinari Takayanagi ,  Masataka Matsui ,  Yasuo Unekawa ,  Tetsu Nagamatsu

发明人： Fumiyuki Yamane ,  Tadahiro Kuroda ,  Toshinari Takayanagi ,  Masataka Matsui ,  Yasuo Unekawa ,  Tetsu Nagamatsu

IPC分类号： G11C11/412 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

CPC分类号： G11C11/419

摘要： A semiconductor memory includes a memory cell including inverters (IN1, IN2), control transistors (T3, T4) that control the potential of a ground side terminal (N3) connected to the memory cell, and transfer transistors T1 and T2 that control transfer of data from bit lines (BL, /BL) to the memory cell. In writing data, the control transistors raise the potential of the ground side terminal (N3) to be higher than the ground potential by a predetermined potential. After the transfer transistors transfer data having a potential difference smaller than a potential difference between the power supply potential and the ground potential from the bit lines (BL, /BL) to the memory cell, and cause the memory cell to hold the data, the potential of the ground side terminal (N3) is decreased to the ground potential to write data. Since data written in the memory cell suffices to have a potential difference smaller than the potential difference between the power supply potential and the ground potential, the time required to drive the bit line having a large load capacitance is shortened, the power consumption is decreased, and the power consumption necessary for writing data in the memory cell is reduced.

摘要翻译： 半导体存储器包括：存储单元，包括反相器（IN1，IN2），控制与存储单元连接的接地侧端子（N3）的电位的控制晶体管（T3，T4）;以及控制晶体管T1和T2， 从位线（BL，/ BL）到存储单元的数据。 在写入数据时，控制晶体管将地侧端子（N3）的电位提高到高于接地电位预定电位。 在转移晶体管将具有比位线（BL，/ BL）的电源电位和接地电位之间的电位差的电位差的数据传送到存储单元之后，使存储单元保持数据， 接地侧端子（N3）的电位降低到接地电位以写入数据。 由于写入存储单元的数据足以具有比电源电位和接地电位之间的电位差小的电位差，所以驱动具有大负载电容的位线所需的时间缩短，功耗降低， 并且减少了在存储单元中写入数据所需的功耗。

公开(公告)号：US5965922A

公开(公告)日：1999-10-12

申请号：US919822

申请日：1997-08-29

申请人： Masataka Matsui

发明人： Masataka Matsui

IPC分类号： G11C11/412 ,  H01L27/11

CPC分类号： H01L27/11 ,  G11C11/412 ,  Y10S257/903

摘要： The disclosed semiconductor memory cell can be formed in accordance with the standard process for the logic LSI, so that the manufacturing cost can be reduced and an increased node capacitance can be secured. The drain diffusion layer (D1) of the latch transistor (M1) for constituting the latch of the memory cell is connected to a portion in the first metal layer through the contact (C1); the source diffusion layer (S1) of the latch transistor (M1) is the grounded wire connected to the first metal layer wire through the contacts (C3 and C3a); the poly silicon (P1) of the latch transistor (M1) is connected to the first metal layer wire or the second metal layer wire through the contact (C2); the first metal layer and the second metal layer are connected to each other by the through hole (V1) formed being overlapped with the contact (C3); the gate of the select transistor (M2) having the source connected to the drain diffusion layer (D1) of the latch transistor (M1) is connected to the word line (WL) of the poly silicon layer; the drain of the select transistor (M2) is connected to the first metal layer wiring through the contact (C4) and further connected to the bit lines formed in the second metal layer through the through hole (V2).

摘要翻译： 可以根据逻辑LSI的标准处理形成所公开的半导体存储单元，从而可以降低制造成本并且可以确保增加的节点电容。 用于构成存储单元的锁存器的锁存晶体管（M1）的漏极扩散层（D1）通过触点（C1）连接到第一金属层中的一部分; 锁存晶体管（M1）的源极扩散层（S1）是通过触点（C3和C3a）连接到第一金属层导线的接地线; 锁存晶体管（M1）的多晶硅（P1）通过触点（C2）连接到第一金属层布线或第二金属层布线; 第一金属层和第二金属层通过与接触件（C3）重叠形成的通孔（V1）彼此连接; 具有连接到锁存晶体管（M1）的漏极扩散层（D1）的源极的选择晶体管（M2）的栅极连接到多晶硅层的字线（WL）; 选择晶体管（M2）的漏极通过触点（C4）连接到第一金属层布线，并且还通过通孔（V2）连接到形成在第二金属层中的位线。

公开(公告)号：US5680127A

公开(公告)日：1997-10-21

申请号：US385625

申请日：1995-02-09

申请人： Tetsu Nagamatsu ,  Masataka Matsui

发明人： Tetsu Nagamatsu ,  Masataka Matsui

IPC分类号： G11C11/41 ,  G06F17/10 ,  G06F17/14 ,  G11C8/12 ,  H03M9/00

CPC分类号： G11C8/12 ,  H03M9/00

摘要： A parallel-to-serial conversion device capable of improved space efficiency has a corner turn memory array provided in an input section of the device to perform parallel-to-serial conversion by writing in the row direction of the input section and by reading out in the column direction of the input section, write section for selectively writing data into a first pair of memory cells of said corner turn memory array; and readout section for simultaneously reading data from a second pair of memory cells which are different from the first pair of memory cells.

摘要翻译： 能够提高空间效率的并行到串行转换装置具有设置在装置的输入部分中的转角存储器阵列，以通过在输入部分的行方向上写入并通过读出来执行并行 - 串行转换 输入部分的列方向，用于选择性地将数据写入所述转角存储器阵列的第一对存储单元的写入部分; 以及读出部，用于同时从与第一对存储单元不同的第二对存储单元读取数据。

公开(公告)号：US5309401A

公开(公告)日：1994-05-03

申请号：US979623

申请日：1992-11-19

申请人： Azuma Suzuki ,  Masataka Matsui

发明人： Azuma Suzuki ,  Masataka Matsui

IPC分类号： H01L27/11 ,  G11C7/12 ,  G11C11/409 ,  G11C11/41 ,  G11C11/419 ,  H01L21/8244 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C11/419 ,  G11C7/12

摘要： A static memory device comprises a memory cell array having of a plurality of sections, each including a plurality of memory cells. A selection signal for selecting one section is generated in accordance with a data writing or reading operation. First and second potentials of high level are generated, and one of the potentials are selectively supplied to pairs of bit lines in one of the plurality of sections. In a data writing operation, the pairs of bit lines are precharged to the first potential, e.g., the supply voltage V.sub.cc, and in a data reading operation, the pair of bit lines is precharged to the second potential, e.g., V.sub.cc -2V.sub.f, where V.sub.f is a forward voltage of a diode.

摘要翻译： 静态存储器件包括具有多个部分的存储单元阵列，每个部分包括多个存储器单元。 根据数据写入或读取操作生成用于选择一个部分的选择信号。 产生高电平的第一和第二电位，并且其中一个电位被选择性地提供给多个部分之一中的一对位线。 在数据写入操作中，位线对被预充电到第一电位，例如电源电压Vcc，并且在数据读取操作中，该对位线被预充电到第二电位，例如Vcc-2Vf， 其中Vf是二极管的正向电压。

公开(公告)号：US5294812A

公开(公告)日：1994-03-15

申请号：US38063

申请日：1993-03-26

申请人： Kazuhiko Hashimoto ,  Masataka Matsui ,  Syoichi Asoh

发明人： Kazuhiko Hashimoto ,  Masataka Matsui ,  Syoichi Asoh

IPC分类号： H01L21/02 ,  G01R31/28 ,  H01L21/00 ,  H01L23/544 ,  H01L29/34

CPC分类号： G01R31/2884 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2924/0002

摘要： A semiconductor device capable of performing a failure analysis includes a semiconductor substrate having a plurality of circuit elements, and an identification region provided above the semiconductor substrate so as to record identification information such as position information within wafers, information for wafer numbers, etc. The identification information is given by binary coded patterns, fused patterns of fuse elements, etc.

摘要翻译： 能够执行故障分析的半导体器件包括具有多个电路元件的半导体器件和设置在半导体衬底上方的识别区域，以便记录晶片内的位置信息等识别信息，晶片号码信息等。 识别信息由二进制编码图案，熔丝元件的融合图案等给出。

公开(公告)号：US5268599A

公开(公告)日：1993-12-07

申请号：US766357

申请日：1991-09-26

申请人： Masataka Matsui

发明人： Masataka Matsui

IPC分类号： G11C11/408 ,  G11C11/409 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/092 ,  H03K19/094

CPC分类号： H03K19/01855 ,  H03K19/00384 ,  H03K19/018521

摘要： The present invention provides a buffer circuit, which comprises a CMOS logic gate circuit in which at least one gate input terminal is input from other circuit, a MOS transistor for controlling a threshold voltage, which is inserted in series into a current path between power source electrodes of the CMOS logic gate circuit including MOS transistors connected to the input terminal, and a control circuit for controlling a gate voltage of the MOS transistor for controlling the threshold voltage such that the logic threshold voltage in the input terminal coincides with a predetermined logic threshold voltage without depending on variation in a power supply voltage, temperature, or a manufacturing process. The logic threshold voltage of the buffer circuit can be maintained constantly without depending on variation in the power supply voltage or temperature.

摘要翻译： 本发明提供了一种缓冲电路，其包括CMOS逻辑门电路，其中至少一个栅极输入端从其他电路输入，用于控制阈值电压的MOS晶体管，其串联插入电源之间的电流路径 包括连接到输入端子的MOS晶体管的CMOS逻辑门电路的电极以及用于控制MOS晶体管的栅极电压以控制阈值电压的控制电路，使得输入端子中的逻辑阈值电压与预定的逻辑阈值一致 电压，而不依赖于电源电压，温度或制造过程的变化。 可以恒定地保持缓冲电路的逻辑阈值电压，而不依赖于电源电压或温度的变化。

公开(公告)号：US4916668A

公开(公告)日：1990-04-10

申请号：US330048

申请日：1989-03-29

申请人： Masataka Matsui

发明人： Masataka Matsui

IPC分类号： G11C11/41 ,  G11C8/18 ,  G11C11/418

CPC分类号： G11C8/18 ,  G11C11/418 ,  G11C2207/061

摘要： A memory cell array includes a plurality of static memory cells arranged in a matrix form and selectively controlled by means of word lines to output complementary memory data to paired bit lines. An address transition detecting circuit generates an address transition signal in the form of a monostable pulse having a constant length when detecting the transition of an address signal. A bit line initializing circuit initializes the potentials of the paired bit lines in synchronism with the address transition signal. A pulse width extension circuit sets the pulse width of the address transition signal generated from the address transition detecting circuit to be longer in the write mode than in the readout mode.

公开(公告)号：US4740718A

公开(公告)日：1988-04-26

申请号：US31923

申请日：1987-03-30

申请人： Masataka Matsui

发明人： Masataka Matsui

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/01 ,  H03K19/003 ,  H03K19/082 ,  H03K19/094

CPC分类号： H03K19/09448 ,  H03K19/0136

摘要： A Bi-CMOS logic circuit having a totem pole-type output buffer, a CMOS logic circuit, and a latch circuit. The output buffer comprises a pull-up NPN bipolar transistor and a pull-down NPN bipolar transistor. The CMOS logic circuit controls the base current of the pull-up NPN bipolar transistor. The latch circuit controls the base current of the pull-down NPN bipolar transistor. The latch circuit includes at least two N-type MOSFETs. The first MOSFET has a gate coupled to the input terminal of the CMOS logic circuit, a drain connected to the node of the first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor. The second MOSFET has a drain coupled to the input terminal of the CMOS logic circuit, a gate connected to the node of the first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor.

摘要翻译： 具有图腾柱型输出缓冲器，CMOS逻辑电路和锁存电路的Bi-CMOS逻辑电路。 输出缓冲器包括上拉NPN双极晶体管和下拉NPN双极晶体管。 CMOS逻辑电路控制上拉NPN双极晶体管的基极电流。 锁存电路控制下拉NPN双极晶体管的基极电流。 锁存电路包括至少两个N型MOSFET。 第一MOSFET具有耦合到CMOS逻辑电路的输入端的栅极，连接到第一和第二NPN双极晶体管的节点的漏极和耦合到所述第二NPN双极晶体管的基极的源极。 第二MOSFET具有耦合到CMOS逻辑电路的输入端的漏极，连接到第一和第二NPN双极晶体管的节点的栅极以及耦合到所述第二NPN双极晶体管的基极的源极。