公开(公告)号：US06853029B2

公开(公告)日：2005-02-08

申请号：US10155086

申请日：2002-05-28

申请人： Masayuki Ichige ,  Yuji Takeuchi ,  Michiharu Matsui ,  Atsuhiro Sato ,  Kikuko Sugimae ,  Riichiro Shirota

发明人： Masayuki Ichige ,  Yuji Takeuchi ,  Michiharu Matsui ,  Atsuhiro Sato ,  Kikuko Sugimae ,  Riichiro Shirota

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.

摘要翻译： 半导体器件包括半导体衬底，源极和漏极区，沟道区，栅极绝缘膜，电荷存储层和控制栅电极。 源区和漏区包括第一导电类型的第一杂质。 沟道区域包括第二导电类型的第二杂质。 栅极绝缘膜包括位于沟道区域的至少一部分正上方的区域中的第二杂质。 电荷存储层形成在栅极绝缘膜上。 控制栅电极设置在电荷存储层上。 控制栅电极形成在电荷存储层上，并且通过设置在电荷存储层的一部分上的连接部分电连接到电荷存储层，所述连接部位于栅极绝缘区域的至少一部分的正上方 膜包括第二杂质。

公开(公告)号：US07498630B2

公开(公告)日：2009-03-03

申请号：US11559785

申请日：2006-11-14

申请人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

发明人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.

摘要翻译： 一种非易失性半导体存储器，被配置为包括沿行方向布置的多个字线; 沿垂直于字线的列方向布置的多个位线; 具有沿列方向设置的电荷存储层的存储单元晶体管和存储单元晶体管的电子存储状态，其被配置为由连接到存储单元的多条字线之一控制; 多个第一选择晶体管，每个包括栅极，选择沿列方向设置的存储单元晶体管，其布置在存储单元晶体管的第一端处并与存储单元晶体管相邻; 以及连接到第一选择晶体管的每个栅电极的第一选择栅极线。

公开(公告)号：US07442985B2

公开(公告)日：2008-10-28

申请号：US11283742

申请日：2005-11-22

申请人： Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

发明人： Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11541 ,  H01L27/11543

摘要： An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on the first conductive layer to extend into the element isolating region. A surface of that section of the second conductive layer which is positioned within the element isolating region is exposed, and a third conductive layer is formed on the second conductive layer with a second insulating film interposed therebetween. Further, a contact is electrically connected to an exposed surface of the second conductive layer.

摘要翻译： 在半导体存储器件的外围电路部分中形成用于分离半导体层的元件区域的元件隔离区域，并且第一导电层形成有元件区域，其间插入有第一绝缘膜。 第二导电层形成在第一导电层上以延伸到元件隔离区域中。 位于元件隔离区域内的第二导电层的该部分的表面被暴露，并且在第二导电层上形成第三导电层，其间插入有第二绝缘膜。 此外，触点电连接到第二导电层的暴露表面。

公开(公告)号：US20050105335A1

公开(公告)日：2005-05-19

申请号：US10944910

申请日：2004-09-21

申请人： Kikuko Sugimae ,  Takuya Futatsuyama ,  Riichiro Shirota ,  Masayuki Ichige

发明人： Kikuko Sugimae ,  Takuya Futatsuyama ,  Riichiro Shirota ,  Masayuki Ichige

IPC分类号： G11C16/06 ,  G11C5/02 ,  G11C5/06 ,  G11C8/10 ,  G11C8/12 ,  G11C16/00 ,  G11C16/04 ,  G11C16/08 ,  H01L21/8247 ,  H01L27/00 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C8/12 ,  G11C8/10 ,  G11C16/08

摘要： A semiconductor memory device having: a cell array including bit lines, word lines and memory cells disposed at crossings thereof, plural memory cells being connected in series to constitute a NAND cell unit, plural blocks being arranged, each being constituted by plural NAND cell units arranged in the word line direction; and a row decoder configured to select a block, wherein the row decoder includes: transferring transistor arrays disposed in association with the blocks, in each of which transistors are arranged for transferring word line drive voltages; first decode portions disposed in association with the transferring transistor arrays, which are applied with boosted voltages to selectively drive the transferring transistor arrays; and second decode portions configured to select one of the blocks, each of which is disposed to be shared by adjacent two first decode portions.

摘要翻译： 一种半导体存储器件，具有：包括位线，字线和位于其交叉处的存储单元的单元阵列，多个存储单元串联连接以构成NAND单元单元，多个块被布置，每个由多个NAND单元单元 排列在字线方向; 以及配置为选择块的行解码器，其中所述行解码器包括：传送与所述块相关联地布置的晶体管阵列，其中每个晶体管布置用于传送字线驱动电压; 与传输晶体管阵列相关联地设置的第一解码部分，其被施加升压电压以选择性地驱动传输晶体管阵列; 以及第二解码部分，被配置为选择所述块之一，每个块被布置为由相邻的两个第一解码部分共享。

公开(公告)号：US20050099847A1

公开(公告)日：2005-05-12

申请号：US11008531

申请日：2004-12-10

申请人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

发明人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

IPC分类号： G11C16/00 ,  G06K17/00 ,  G06K19/077 ,  G11C11/34 ,  G11C14/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.

公开(公告)号：US06590255B2

公开(公告)日：2003-07-08

申请号：US09916595

申请日：2001-07-30

申请人： Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

发明人： Masayuki Ichige ,  Riichiro Shirota ,  Yuji Takeuchi ,  Kikuko Sugimae

IPC分类号： H01L29788

CPC分类号： H01L27/11526 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11541 ,  H01L27/11543

摘要： An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on the first conductive layer to extend into the element isolating region. A surface of that section of the second conductive layer which is positioned within the element isolating region is exposed, and a third conductive layer is formed on the second conductive layer with a second insulating film interposed therebetween. Further, a contact is electrically connected to an exposed surface of the second conductive layer.

公开(公告)号：US07504294B2

公开(公告)日：2009-03-17

申请号：US10881180

申请日：2004-07-01

申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

IPC分类号： H01L21/8238

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

公开(公告)号：US07417281B2

公开(公告)日：2008-08-26

申请号：US11733488

申请日：2007-04-10

申请人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

发明人： Kikuko Sugimae ,  Hiroyuki Kutsukake ,  Masayuki Ichige ,  Michiharu Matsui ,  Yuji Takeuchi ,  Riichiro Shirota

IPC分类号： H01L29/94

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

摘要翻译： 半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫 在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能 仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

公开(公告)号：US07361951B2

公开(公告)日：2008-04-22

申请号：US11259142

申请日：2005-10-27

申请人： Riichiro Shirota ,  Kikuko Sugimae ,  Masayuki Ichige ,  Atsuhiro Sato ,  Hiroaki Hazama

发明人： Riichiro Shirota ,  Kikuko Sugimae ,  Masayuki Ichige ,  Atsuhiro Sato ,  Hiroaki Hazama

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11536

摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.

摘要翻译： 半导体存储器件包括半导体衬底，形成在半导体衬底中并包括用于隔离元件区的厚元件隔离绝缘膜的元件隔离区，设置在半导体衬底中的元件区域上的自对准的第一栅电极 在元件隔离区域中，设置在第一栅电极上的绝缘膜的第二栅极电极和形成在元件隔离区域上的电阻元件，电阻元件和第二栅电极由相同的导电膜形成。

公开(公告)号：US07141474B2

公开(公告)日：2006-11-28

申请号：US11008531

申请日：2004-12-10

申请人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

发明人： Masayuki Ichige ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

摘要： A method of fabricating a nonvolatile semiconductor memory including the steps of: sequentially forming a gate insulating layer and a first conductive layer of a floating gate on a semiconductor substrate; depositing an inter-gate insulating layer; forming an opening in a part of the inter-gate insulating layer; depositing a control gate electrode on the inter-gate insulating layer and an exposed portion of the first conductive layer by the opening; and forming the gate electrodes of the memory cell transistors and the gate electrodes of the select transistors by utilizing the etching processes of the control gate electrode, the inter-gate insulating layer and the first conductive layer, wherein the select transistors include at least a part of the exposed portion of the first conductive layer.

摘要翻译： 一种制造非易失性半导体存储器的方法，包括以下步骤：在半导体衬底上依次形成栅极绝缘层和浮置栅极的第一导电层; 沉积栅极间绝缘层; 在所述栅极绝缘层的一部分中形成开口; 通过所述开口在所述栅极间绝缘层上沉积控制栅极电极和所述第一导电层的暴露部分; 以及通过利用所述控制栅电极，所述栅极间绝缘层和所述第一导电层的蚀刻工艺，形成所述存储单元晶体管的栅电极和所述选择晶体管的栅电极，其中所述选择晶体管至少包括一部分 的第一导电层的暴露部分。