公开(公告)号：US08943384B2

公开(公告)日：2015-01-27

申请号：US13445591

申请日：2012-04-12

申请人： Deepak Sridhara ,  Arvind Sridharan ,  Ara Patapoutian

发明人： Deepak Sridhara ,  Arvind Sridharan ,  Ara Patapoutian

IPC分类号： G11C29/00 ,  H03M13/00

CPC分类号： G06F11/1048 ,  G11C11/5642 ,  H03M13/1111 ,  H03M13/2957 ,  H03M13/3707 ,  H03M13/6325 ,  H03M13/6511 ,  H03M13/6577

摘要： A method for re-using a soft decoder involves receiving soft data and hard data from memory cells in a memory device, mapping the soft data to a first set of soft information, mapping the hard data to a second set of soft information, and using the soft decoder to decode both the first set and second set of soft information.

摘要翻译： 用于重新使用软解码器的方法包括从存储器设备中的存储器单元接收软数据和硬数据，将软数据映射到第一组软信息，将硬数据映射到第二组软信息，并使用 软解码器解码第一组和第二组软信息。

公开(公告)号：US08693257B2

公开(公告)日：2014-04-08

申请号：US13275598

申请日：2011-10-18

申请人： Arvind Sridharan ,  Ara Patapoutian

发明人： Arvind Sridharan ,  Ara Patapoutian

IPC分类号： G11C16/10

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/3418

摘要： Approaches for operating a memory device comprising memory cells are disclosed. Optimal values for one or more of programming voltages used to program memory cells of the memory device and read reference voltages used to read the memory cells are determined using a mutual information function, I(X; Y), where X represents data values programmed to the memory cells and Y represents data values read from the memory cells. The read reference and/or programming voltages used for reading and/or programming the memory cells are adjusted using the optimal values.

摘要翻译： 公开了用于操作包括存储器单元的存储器件的方法。 使用用于对存储器件的存储器单元编程的一个或多个编程电压和用于读取存储器单元的读取参考电压的最佳值使用互信息函数I（X; Y）确定，其中X表示被编程为 存储单元，Y表示从存储器单元读取的数据值。 用于读取和/或编程存储器单元的读取参考和/或编程电压使用最佳值进行调整。

公开(公告)号：US08547743B2

公开(公告)日：2013-10-01

申请号：US13170501

申请日：2011-06-28

申请人： Bengt Anders Ulriksson ,  Ara Patapoutian

发明人： Bengt Anders Ulriksson ,  Ara Patapoutian

IPC分类号： G11C16/04

CPC分类号： G11C16/3404 ,  G11C16/3418

摘要： A read error is determined that affects a page of solid-state, non-volatile memory. The page is associated with a selected word line that crosses a plurality of NAND strings coupled to respective grounds and bit lines. Word lines of the memory are ordered from a lower end proximate the ground to a higher end proximate the bit lines. Cumulative background charges each associated with one of the memory cells of the page are determined. The cumulative background charges are based on charge levels of respective cells of a plural subset of the word lines that are lower in order than the selected word line. A recovery operation is performed on the page using the cumulative background charges.

摘要翻译： 确定影响固态，非易失性存储器页面的读取错误。 该页面与选定的字线相关联，该字线跨越耦合到相应接地和位线的多个NAND串。 存储器的字线从靠近地面的下端排列到靠近位线的较高端。 确定与页面的一个存储单元相关联的累积背景费用。 累积背景电荷是基于与选择的字线相比顺序低的字线的多个子集的各个单元的电荷电平。 使用累积背景费用在页面上执行恢复操作。

公开(公告)号：US20130232291A1

公开(公告)日：2013-09-05

申请号：US13410072

申请日：2012-03-01

申请人： Ara Patapoutian ,  Bernie Rub

发明人： Ara Patapoutian ,  Bernie Rub

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1032 ,  G11C11/56 ,  G11C11/5621 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26 ,  G11C2013/0054

摘要： Various embodiments of the present disclosure are generally directed to the accessing of data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a transfer command is received to transfer selected data between a control module and a memory module. The transfer command specifies a target address in the memory module and a sense threshold vector associated with the selected data. The sense threshold vector in the received transfer command is used to sense a programmed state of at least one solid-state memory cell at the target address responsive to the received transfer command. The transfer command may be a read or write command.

摘要翻译： 本公开的各种实施例通常涉及对存储器（例如但不限于闪速存储器阵列）中的数据的访问。 根据一些实施例，接收传送命令以在控制模块和存储器模块之间传送所选择的数据。 传输命令指定存储器模块中的目标地址和与所选数据相关联的感测阈值向量。 接收到的传送命令中的感测阈值向量用于响应于所接收的传送命令来感测目标地址上的至少一个固态存储器单元的编程状态。 传输命令可以是读或写命令。

公开(公告)号：US20130094290A1

公开(公告)日：2013-04-18

申请号：US13275675

申请日：2011-10-18

申请人： Arvind Sridharan ,  Ara Patapoutian

发明人： Arvind Sridharan ,  Ara Patapoutian

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/28 ,  G11C16/349 ,  G11C29/00

摘要： Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells.

摘要翻译： 将固态非易失性存储器的单元分配给多个组中的一个。 鉴于从单元读取的实际符号，每个组由存储在单元中的预期符号定义。 基于组内的单元计数，可以确定参考电压的偏移将降低单元的集合误码率。 该移位可以应用于影响单元的数据访问操作。

公开(公告)号：US08166364B2

公开(公告)日：2012-04-24

申请号：US12185437

申请日：2008-08-04

申请人： Ara Patapoutian ,  Arvind Sridharan

发明人： Ara Patapoutian ,  Arvind Sridharan

IPC分类号： G06F11/00

CPC分类号： H03M13/1111 ,  H03M13/2957 ,  H03M13/3707 ,  H03M13/6343

摘要： A decoding system comprises an iterative decoder that utilizes parity constraints to iteratively decode a block of data that consists of multiple code words, and a processor that controls the iterative decoder to selectively remove a subset of the parity constraints for a number of decoder iterations and include one or more of the selectively removed parity constraints in other decoder iterations.

摘要翻译： 解码系统包括迭代解码器，其使用奇偶校验约束来迭代地解码由多个码字组成的数据块，以及处理器，其控制迭代解码器以选择性地去除多个解码器迭代的奇偶校验约束的子集，并且包括 其他解码器迭代中的一个或多个选择性移除的奇偶校验约束。

公开(公告)号：US08156409B2

公开(公告)日：2012-04-10

申请号：US12040230

申请日：2008-02-29

申请人： Ara Patapoutian ,  Rose Y. Shao ,  Arvind Sridharan

发明人： Ara Patapoutian ,  Rose Y. Shao ,  Arvind Sridharan

IPC分类号： H03M13/00

CPC分类号： H03M13/112 ,  H03M13/3707 ,  H03M13/6502 ,  H03M13/6583

摘要： In accordance with one or more embodiments, a decoder may determine whether a lowest reliability value of a plurality of codeword bits that correspond to a particular output reliability value for a particular constraint node of a parity-check matrix is greater than a threshold value (e.g., an offset), and if so, selectively applies a modified min-sum approximation constraint node update with a reliability value modification (e.g., an offset or normalized min-sum approximation).

摘要翻译： 根据一个或多个实施例，解码器可以确定对应于奇偶校验矩阵的特定约束节点的特定输出可靠性值的多个码字比特的最低可靠性值是否大于阈值（例如， ，偏移），如果是，则选择性地应用具有可靠性值修改（例如，偏移或归一化最小和近似）的经修改的最小和近似约束节点更新。

公开(公告)号：US08130553B2

公开(公告)日：2012-03-06

申请号：US12629481

申请日：2009-12-02

申请人： Bruce D. Buch ,  Ara Patapoutian ,  Bengt A. Ulriksson ,  Bernardo Rub

发明人： Bruce D. Buch ,  Ara Patapoutian ,  Bengt A. Ulriksson ,  Bernardo Rub

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C16/349

摘要： This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability.

摘要翻译： 本公开涉及固态存储器（例如闪速存储器）的低磨损操作的系统和方法。 在一个示例中，控制器耦合到存储器并且适于在数据存储设备的使用过程中动态地调整编程阈值，使得从存储在数据存储单元中的读取数据的信噪比不小于 使用增强的错误检测功能恢复数据所需的最小数量。

公开(公告)号：US20090231745A1

公开(公告)日：2009-09-17

申请号：US12048830

申请日：2008-03-14

申请人： Raman Chatapuram Venkataramani ,  Alexander Vasilievich Kuznetsov ,  Ara Patapoutian

发明人： Raman Chatapuram Venkataramani ,  Alexander Vasilievich Kuznetsov ,  Ara Patapoutian

IPC分类号： G11B5/09

CPC分类号： G11B20/10009 ,  G11B20/10287 ,  G11B20/10296 ,  G11B2220/2516

摘要： In a particular embodiment, a channel detector is disclosed that includes a programmable look-up table (LUT) to relate user bits to channel bits. The programmable LUT is adapted to be implemented on a state trellis of arbitrary radix. The channel detector further includes a sectional precoder coupled to a channel and having access to the programmable LUT. The sectional precoder is adapted to map channel bits to user bits and vice versa using a programmable LUT.

摘要翻译： 在特定实施例中，公开了一种信道检测器，其包括用于将用户比特与信道比特相关联的可编程查询表（LUT）。 可编程LUT适于在任意基数的状态网格上实现。 信道检测器还包括耦合到信道并且访问可编程LUT的分段预编码器。 分段预编码器适于使用可编程LUT将通道位映射到用户位，反之亦然。

公开(公告)号：US07342734B1

公开(公告)日：2008-03-11

申请号：US11011998

申请日：2004-12-14

申请人： Ara Patapoutian ,  Michael Leis ,  Bruce Buch

发明人： Ara Patapoutian ,  Michael Leis ,  Bruce Buch

IPC分类号： G11B5/09

CPC分类号： G11B5/59688 ,  G11B5/59655

摘要： A disk drive includes a rotatable data storage disk, a transducer, an actuator, and a servo burst demodulator. The rotatable data storage disk includes a plurality of servo burst patterns thereon. The plurality of servo burst patterns are substantially radially aligned to each other, and radially adjacent ones of the servo burst patterns are configured to generate contributions to a read signal that are substantially orthogonal to each other. The transducer is configured to read the servo burst patterns on the disk to generate the read signal. The actuator is configured to position the transducer relative to the disk. The servo burst demodulator is configured to identify a separate contribution to the read signal from the radially adjacent servo burst patterns. The servo burst demodulator may be configured to generate transducer position information based on the identified separate contribution to the read signal from the radially adjacent servo burst patterns.

摘要翻译： 磁盘驱动器包括可旋转数据存储盘，换能器，致动器和伺服突发解调器。 可旋转数据存储盘在其上包括多个伺服突发图案。 多个伺服突发图案基本上彼此径向对准，并且径向相邻的伺服突发图案被配置为产生对彼此基本正交的读取信号的贡献。 换能器被配置为读取盘上的伺服脉冲串图案以产生读取信号。 致动器被配置成相对于盘定位换能器。 伺服脉冲串解调器被配置为识别来自径向相邻的伺服脉冲串图案对读取信号的单独贡献。 伺服突发解调器可以被配置为基于从径向相邻的伺服脉冲串图案对所读取的信号所识别的单独贡献来生成换能器位置信息。