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公开(公告)号：US06954100B2
公开(公告)日：2005-10-11
申请号：US10660847
申请日：2003-09-12
CPC分类号： H03K3/356113
摘要： A level shifter for an integrated circuit. In one embodiment, the level shifter is a bi-directional level shifter with a signal terminal located in each voltage domain that can be utilized as input or output terminal. In some embodiments, the level shifter includes transistors for cutting off the flow of current between domain power supplies when the input terminals are at a particular state. In one embodiment, only one signal line of the level shifter crosses a domain boundary.
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公开(公告)号：US5703506A
公开(公告)日：1997-12-30
申请号：US578726
申请日：1995-12-26
IPC分类号： H04B10/158 , H04L25/06 , H04Q9/00 , G08G1/01
CPC分类号： H04B10/697 , H04L25/062
摘要： A signal processing circuit (10) performs a sample and hold (16) of an input signal (14) and stores a maximum value of the input signal (18). A guardband signal (21) is developed that is less than the maximum value that is stored. The input signal is compared to the guardband signal to determine if the input signal is above or below the guardband signal. A threshold signal (25) is developed by taking a percentage of the maximum value that is stored. The input signal is compared to the threshold signal to regenerate the input waveform. If the input signal is below the guardband signal and above the threshold signal, the sample and hold circuit is reset to acquire a new maximum value of the input signal so that a new threshold can be used for regenerating the input signal.
摘要翻译： 信号处理电路（10）执行输入信号（14）的采样和保持（16）并存储输入信号（18）的最大值。 开发出小于存储的最大值的保护带信号（21）。 将输入信号与保护频带信号进行比较，以确定输入信号是否高于或低于保护频带信号。 通过获取存储的最大值的百分比来开发阈值信号（25）。 将输入信号与阈值信号进行比较，以重新生成输入波形。 如果输入信号低于保护带信号并且高于阈值信号，则采样和保持电路被复位以获取输入信号的新的最大值，使得可以使用新的阈值来再生输入信号。
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33.发明授权
公开(公告)号：US5522002A
公开(公告)日：1996-05-28
申请号：US370692
申请日：1995-01-10
IPC分类号： G02B6/42
CPC分类号： G02B6/4292 , G02B6/4249 , G02B6/4246
摘要： A substrate having a photonic device mounted thereon with a working portion that is operably connected to at least one electrical lead. A molded optical portion having a surface for light signal to enter and to exit is formed that encapsulates the substrate, the photonic device, and a portion of the first and second electrical lead. An optical connector is formed to plug into the molded optical portion to connect a fiber bundle thereto and the optical portion is electrically connected to an interconnect module.
摘要翻译： 一种具有安装在其上的光子器件的衬底，其具有可操作地连接到至少一个电引线的工作部分。 形成具有用于光信号进入和退出的表面的模制光学部分，其封装基板，光子器件以及第一和第二电引线的一部分。 光连接器被形成为插入到模制的光学部分中以将光纤束连接到其上，并且光学部分电连接到互连模块。
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公开(公告)号：US5304949A
公开(公告)日：1994-04-19
申请号：US989671
申请日：1992-12-14
摘要： A common base amplifier (29) has an input (31) and an output (32). A transistor (33) has an emitter coupled to the input (31) of the amplifier (29), a collector coupled to the output (32) of the amplifier (29), and a base coupled to a voltage reference (34) provides low input impedance and unity current gain. A control circuit (38) controls a first bias circuit (36) and a second bias circuit (37). The second bias circuit (37) is coupled to the collector of the transistor (33) and provides a bias current for the transistor (33) while transistor (33) outputs the bias current which is received by the first bias circuit (36). Control circuit (38) determines the current magnitude for both the first bias circuit (36) and the second bias circuit (37) and ensures that the current magnitudes are maintained at a fixed ratio.
摘要翻译： 公共基极放大器（29）具有输入端（31）和输出端（32）。 晶体管（33）具有耦合到放大器（29）的输入（31）的发射极，耦合到放大器（29）的输出（32）的集电极，耦合到电压基准（34）的基极提供 低输入阻抗和单位电流增益。 控制电路（38）控制第一偏置电路（36）和第二偏置电路（37）。 第二偏置电路（37）耦合到晶体管（33）的集电极，并为晶体管（33）提供偏置电流，同时晶体管（33）输出由第一偏置电路（36）接收的偏置电流。 控制电路（38）确定第一偏置电路（36）和第二偏置电路（37）两者的电流幅值，并确保电流幅值保持在固定比例。
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公开(公告)号：US5703504A
公开(公告)日：1997-12-30
申请号：US578727
申请日：1995-12-26
CPC分类号： H03F3/08 , H03F3/3432 , H03F3/45982 , H03G3/345
摘要： A signal processing circuit (10) generates a bias signal (27) that is used for biasing a comparator (26). An input signal (14) is compared to the bias signal (27) in order to reconstruct the input signal (14) on an output of the comparator. The bias signal (27) is generated by selecting the larger of a percent of the input signal (23) or an offset signal (24) that is larger than a minimum value of the input signal.
摘要翻译： 信号处理电路（10）产生用于偏置比较器（26）的偏置信号（27）。 将输入信号（14）与偏置信号（27）进行比较，以便重建比较器的输出端上的输入信号（14）。 偏置信号（27）通过选择输入信号（23）的百分比中的较大者或大于输入信号的最小值的偏移信号（24）来产生。
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公开(公告)号：US5446814A
公开(公告)日：1995-08-29
申请号：US355457
申请日：1994-12-13
CPC分类号： H01L24/73 , G02B6/30 , G02B6/4214 , G02B6/4227 , G02B6/43 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/12042 , H01L2924/12043
摘要： A molded reflective optical waveguide module is provided. A molded first optical portion having a fist surface or a major surface is formed. A core region having a first end and a second end is disposed into the first surface of the molded first optical portion with the first end of the core region terminating in a surface having an angle. A second molded optical portion having electrical traces and photonic devices can be applied to the molded first optical portion.
摘要翻译： 提供了一种模制的反射光波导模块。 形成具有第一表面或主表面的模制的第一光学部分。 具有第一端和第二端的芯区域设置在模制的第一光学部分的第一表面中，芯区域的第一端终止于具有一定角度的表面。 具有电迹线和光子器件的第二模制光学部分可以应用于模制的第一光学部分。
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公开(公告)号：US09198224B2
公开(公告)日：2015-11-24
申请号：US13366347
申请日：2012-02-05
申请人： John J. Vaglica , Christopher K. Y. Chun , Jose G. Corleto-Mena , Arnaldo R. Cruz , Jianping Tao , Mieu V. Vu , Mark E. Elledge , Charbel Khawand , Arthur M. Goldberg , David J. Hayes
发明人： John J. Vaglica , Christopher K. Y. Chun , Jose G. Corleto-Mena , Arnaldo R. Cruz , Jianping Tao , Mieu V. Vu , Mark E. Elledge , Charbel Khawand , Arthur M. Goldberg , David J. Hayes
CPC分类号： H04W84/08
摘要： A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.
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公开(公告)号：US08223910B2
公开(公告)日：2012-07-17
申请号：US11917111
申请日：2005-06-10
IPC分类号： H04L7/00
CPC分类号： G06F13/4291 , Y02D10/14 , Y02D10/151
摘要： A device and a method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller and to at least one component; defining a short synchronization period; processing at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining at least the clock line in a low power mode when the data line is substantially idle.
摘要翻译： 一种用于帧同步的设备和方法，所述方法包括在通过连接到媒体接入控制器的数据线和至少一个组件的信息传输期间在时钟线上提供高频时钟信号; 定义短的同步时间段; 处理在短同步周期期间通过数据线路传送的至少一个信号，以确定同步误差的存在; 以及当所述数据线基本为空闲时，至少将所述时钟线保持在低功率模式。
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公开(公告)号：US08131316B2
公开(公告)日：2012-03-06
申请号：US12606044
申请日：2009-10-26
申请人： John J. Vaglica , Christopher K. Y. Chun , Jose G. Corleto-Mena , Arnaldo R. Cruz , Jianping Tao , Mieu V. Vu , Mark E. Elledge , Charbel Khawand , Arthur M. Goldberg , David J. Hayes
发明人： John J. Vaglica , Christopher K. Y. Chun , Jose G. Corleto-Mena , Arnaldo R. Cruz , Jianping Tao , Mieu V. Vu , Mark E. Elledge , Charbel Khawand , Arthur M. Goldberg , David J. Hayes
CPC分类号： H04W84/08
摘要： A cellular mobile station including a modem processor and memory. The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.
摘要翻译： 包括调制解调器处理器和存储器的蜂窝移动站。 存储器包括用于调制解调器处理器执行第1层处理器操作，第2层处理器操作和第3层处理器操作的指令。 调制解调器处理器执行指令，以便根据蜂窝通信协议对蜂窝移动站执行通信数据的处理器操作。 在一个示例中，移动站包括不同级别的存储器以提供不同的确定性访问时间。
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公开(公告)号：US07365596B2
公开(公告)日：2008-04-29
申请号：US10819383
申请日：2004-04-06
IPC分类号： G05F1/10
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F13/4072 , Y02D10/126 , Y02D10/128 , Y02D10/151 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.
摘要翻译： 通过使用从电路块或电路块的一部分去除功率的功率门控，可以降低功耗，以减少漏电流。 一个实施例使用修改的状态保持触发器，其能够在电力被去除或部分地从电路中移除时保持状态。 另一实施例使用修改状态保持缓冲器，其能够在电力被去除或部分地从电路中移除时保持状态。 状态保持触发器和缓冲器可以用于允许状态保持同时仍然减少漏电流。 还公开了使用例如状态保持触发器和缓冲器来降低功率和保持状态的各种方法。 例如，软件，硬件或软件和硬件方法的组合可以用于在保持状态的同时进入深度睡眠或空闲模式。
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