中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

256 records (took 0.023 seconds)

    TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE
    31.
    发明申请
    TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE 审中-公开

    公开(公告)号：US20190362789A1

    公开(公告)日：2019-11-28

    申请号：US16419821

    申请日：2019-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Andrea Redaelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Mario Allegra ,  Paolo Fantini

    IPC: G11C13/00 ,  G11C11/56 ,  H01L27/24

    Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

    Three dimensional memory arrays
    32.
    发明授权
    Three dimensional memory arrays 有权

    公开(公告)号：US10461125B2

    公开(公告)日：2019-10-29

    申请号：US15689155

    申请日：2017-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Andrea Redaelli ,  Fabio Pellizzer ,  Innocenzo Tortorelli

    IPC: H01L27/24 ,  H01L45/00 ,  H01L27/115

    Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.

    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
    33.
    发明申请
    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME 审中-公开

    公开(公告)号：US20190288194A1

    公开(公告)日：2019-09-19

    申请号：US16360756

    申请日：2019-03-21

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Andrea Ghetti

    IPC: H01L45/00 ,  H01L27/24

    Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.

    APPARATUSES AND METHODS INCLUDING MEMORY AND OPERATION OF SAME
    34.
    发明申请
    APPARATUSES AND METHODS INCLUDING MEMORY AND OPERATION OF SAME 审中-公开

    公开(公告)号：US20190027218A1

    公开(公告)日：2019-01-24

    申请号：US16137950

    申请日：2018-09-21

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Innocenzo Tortorelli ,  Stephen Tang ,  Christina Papagianni

    IPC: G11C13/00 ,  G11C11/56

    Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

    Apparatuses including memory cells and methods of operation of same
    35.
    发明授权
    Apparatuses including memory cells and methods of operation of same 有权

    公开(公告)号：US10157670B2

    公开(公告)日：2018-12-18

    申请号：US15338154

    申请日：2016-10-28

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Innocenzo Tortorelli ,  Andrea Redaelli ,  Fabio Pellizzer

    IPC: G11C11/00 ,  G11C13/00

    Abstract: Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities.

    Program operations in memory
    36.
    发明授权
    Program operations in memory 有权

    公开(公告)号：US10157650B1

    公开(公告)日：2018-12-18

    申请号：US15659728

    申请日：2017-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Marco Sforzin ,  Paolo Amato ,  Innocenzo Tortorelli ,  Marco Dallabora

    IPC: G11C5/02 ,  G11C7/10

    Abstract: The present disclosure includes apparatuses and methods related to program operations in memory. An example apparatus can perform a program operation on an array of memory cells by applying a first program signal to a first portion of the array of memory cells that are to remain in a first state in response to the program operation, wherein the first program signal programs memory cells to a second state and then to the first state.

    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
    40.
    发明申请
    CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME 审中-公开

    公开(公告)号：US20180006217A1

    公开(公告)日：2018-01-04

    申请号：US15689256

    申请日：2017-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Andrea Ghetti

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

    Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.

Patent Agency Ranking