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    DETERMINING OFFSETS FOR MEMORY READ OPERATIONS
    31.
    发明申请
    DETERMINING OFFSETS FOR MEMORY READ OPERATIONS 有权

    公开(公告)号：US20240404604A1

    公开(公告)日：2024-12-05

    申请号：US18733187

    申请日：2024-06-04

    Applicant: Micron Technology, Inc.

    Inventor： Jie Zhou ,  Xiangang Luo ,  Min Rui Ma ,  Guang Hu

    IPC: G11C16/26 ,  G11C29/02 ,  G11C29/52

    Abstract: Methods, systems, and devices for determining offsets for memory read operations are described. In response to a threshold quantity of pages failing initial reads but being successfully read using a same reference adjustment during re-reads, the offset responsible for the adjustment may be used as a first-applied offset for subsequent re-reads or a baseline offset for subsequent initial reads. After the initial reads begin using the reference adjustment, if a threshold quantity of pages fail initial reads, the offset used for the initial read may be adjusted to be the offset used to perform the successful re-reads. If an updated offset to use a baseline is not identified, the baseline offset may be cleared so the original reference may again be used without adjustment for initial reads.

    MANAGING ALLOCATION OF HALF GOOD BLOCKS
    32.
    发明申请
    MANAGING ALLOCATION OF HALF GOOD BLOCKS 有权

    公开(公告)号：US20240370181A1

    公开(公告)日：2024-11-07

    申请号：US18651781

    申请日：2024-05-01

    Applicant: Micron Technology, Inc.

    Inventor： Yuqi Zhu ,  Guang Hu ,  Ting Luo ,  Xiangang Luo

    IPC: G06F3/06

    Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to dynamically allocate blocks from a free block pool. The controller generates a free block pool that includes a collection of full blocks and a collection of partial good blocks (PGBs) of a set of memory components, a size of a full block in the collection of full blocks corresponding to a combination of two or more PGBs of the collection of PGBs. The controller receives a request to write data. The controller allocates an individual full block from the collection of full blocks or an individual PGB from the collection of PGBs based on determining whether the request to write the data has been received from the host device or the controller of the memory sub-system.

    PROGRAMMING ERASE BLOCKS COUPLED TO A SAME STRING
    34.
    发明公开
    PROGRAMMING ERASE BLOCKS COUPLED TO A SAME STRING 审中-公开

    公开(公告)号：US20240311057A1

    公开(公告)日：2024-09-19

    申请号：US18606670

    申请日：2024-03-15

    Applicant: Micron Technology, Inc.

    Inventor： Daniel J. Hubbard ,  Kishore K. Muchherla ,  Hong Lu ,  Xiangang Luo ,  Akira Goda

    IPC: G06F3/06

    CPC classification number: G06F3/0679 ,  G06F3/0614 ,  G06F3/0659

    Abstract: A method can comprise receiving data corresponding to a sequence of write commands to write the data to a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block having a first programming characteristic; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block having a second programming characteristic. The method can further comprise writing data sequentially to the first erase blocks of the plurality of strings and the second erase blocks of the plurality of strings in an interleaved manner by: writing a first portion of the data to one or more first erase blocks of the plurality of strings; and writing, subsequent to writing the first portion of the data to the one or more first erase blocks, a second portion of the data to one or more second erase blocks of the plurality of strings.

    DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
    35.
    发明公开
    DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING 审中-公开

    公开(公告)号：US20240168878A1

    公开(公告)日：2024-05-23

    申请号：US18386746

    申请日：2023-11-03

    Applicant: Micron Technology, Inc.

    Inventor： Akira Goda ,  Kishore K. Muchherla ,  Shyam Sunder Raghunathan ,  Leo Raimondo ,  Jung Sheng Hoei ,  Xiangang Luo ,  Ashutosh Malshe ,  Jianmin Huang

    IPC: G06F12/02

    CPC classification number: G06F12/0246

    Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to: perform a programming operation on the first group of memory cells of the first erase block; monitor a quantity of programming and/or erase operations performed on the second group of memory cells subsequent to the programming of the first group of memory cells; and perform an action on the first erase block responsive to the quantity of programming and/or erase operations performed on the second group of memory cells meeting a criteria.

    Media management on power-up
    36.
    发明授权
    Media management on power-up 有权

    公开(公告)号：US11822796B2

    公开(公告)日：2023-11-21

    申请号：US17857780

    申请日：2022-07-05

    Applicant: Micron Technology, Inc.

    Inventor： Tao Liu ,  Xiangang Luo

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0679

    Abstract: A method includes detecting a power-up event associated with a memory sub-system comprising a plurality of blocks of memory cells having blocks of memory cells associated therewith, responsive to detecting the power-up event and prior to receipt of signaling indicative of a host initiation sequence, determining that a block of memory cells associated with a respective block among the plurality of blocks of memory cells is an open virtual block of memory cells, determining that the respective block associated with the open virtual block of memory cells exhibits greater than a threshold health characteristic value, and selectively performing a media management operation of a respective block of memory cells associated with the open virtual block of memory cells in response to the determination that the respective block exhibits greater than the threshold health characteristic value.

    Read error recovery
    40.
    发明授权
    Read error recovery 有权

    公开(公告)号：US11775181B2

    公开(公告)日：2023-10-03

    申请号：US17708735

    申请日：2022-03-30

    Applicant: Micron Technology, Inc.

    Inventor： Xiangang Luo ,  Harish Reddy Singidi ,  Ting Luo ,  Kishore Kumar Muchherla

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

    Abstract: Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system, the error recovery data structure storing indications that specific CWs are correctable or not correctable by specific error handing (EH) steps of a set of multiple EH steps, and determine an order of EH steps for the storage system based on the error recovery data structure. Maintaining the error recovery data structure can include determining if each CW of the set of CWs is correctable by a specific EH step, storing indications of CWs determined correctable by the specific EH step in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.

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