公开(公告)号：US20240257841A1

公开(公告)日：2024-08-01

申请号：US18634074

申请日：2024-04-12

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C5/06 ,  G06F13/16 ,  G11C11/22 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/56

CPC classification number: G11C5/063 ,  G06F13/1668 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/4091 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/4087 ,  G11C11/565 ,  G11C11/5657

Abstract: Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.

公开(公告)号：US20240249758A1

公开(公告)日：2024-07-25

申请号：US18623355

申请日：2024-04-01

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L. Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12

CPC classification number: G11C8/18 ,  G11C7/1096 ,  G11C8/06 ,  G11C8/12

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US11984187B2

公开(公告)日：2024-05-14

申请号：US17569303

申请日：2022-01-05

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Thomas H. Kinsley ,  Baekkyu Choi

IPC: G11C5/06 ,  G06F13/16 ,  G11C11/22 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/56

CPC classification number: G11C5/063 ,  G06F13/1668 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/4091 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/4087 ,  G11C11/565 ,  G11C11/5657

Abstract: Methods and devices for dynamic allocation of a capacitive component in a memory device are described. A memory device may include one or more voltage rails for distributing supply voltages to a memory die. A memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. The capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. The capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.

公开(公告)号：US11966595B2

公开(公告)日：2024-04-23

申请号：US17879476

申请日：2022-08-02

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  Baekkyu Choi ,  Fuad Badrieh

IPC: G06F3/06 ,  G06F1/32 ,  G06F1/3234

CPC classification number: G06F3/0625 ,  G06F1/3275 ,  G06F3/0655 ,  G06F3/0679

Abstract: Methods, systems, and devices for power management for a memory device are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating a set of memory dies of the apparatus based on a supply voltage received by the memory die. The voltage may be distributed to the set of memory dies in the apparatus.

公开(公告)号：US20230018622A1

公开(公告)日：2023-01-19

申请号：US17879476

申请日：2022-08-02

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  Baekkyu Choi ,  Fuad Badrieh

IPC: G06F3/06

Abstract: Methods, systems, and devices for power management for a memory device are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating a set of memory dies of the apparatus based on a supply voltage received by the memory die. The voltage may be distributed to the set of memory dies in the apparatus.

公开(公告)号：US11366505B2

公开(公告)日：2022-06-21

申请号：US16369804

申请日：2019-03-29

Applicant: Micron Technology, Inc.

Inventor： Fuad Badrieh ,  Baekkyu Choi ,  Thomas H. Kinsley

IPC: G06F1/3225 ,  G06F1/3234 ,  G06F3/06

Abstract: Methods, systems, and devices for predictive power management are described. Correlations may be identified between a set of commands performed at the memory device and oscillating voltage patterns, or a resonance frequency, or both. Voltages may be monitored by the memory device and be compared to the identified voltage pattern to mitigate undesirable oscillating voltages and resonance frequency.

公开(公告)号：US20220171547A1

公开(公告)日：2022-06-02

申请号：US17110140

申请日：2020-12-02

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  Baekkyu Choi ,  Fuad Badrieh

IPC: G06F3/06

Abstract: Methods, systems, and devices for memory device power management are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating one or more memory dies of the apparatus based on a supply voltage received by the memory die. The second voltage may be distributed to the one or more other memory dies in the apparatus.

公开(公告)号：US20220035432A1

公开(公告)日：2022-02-03

申请号：US17502458

申请日：2021-10-15

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Thomas H. Kinsley ,  Fuad Badrieh

IPC: G06F1/3225

Abstract: A memory device may include a pin for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit (PMIC). The memory device may bias the pin to a first voltage indicating that a supply voltage is within a target range. The memory device may subsequently determine that a supply voltage is outside the target range and transition the voltage at the pin from the first voltage to a second voltage indicating that the supply voltage is outside the target range. The memory device may select the second voltage based on whether the supply voltage is above or below the target range.

公开(公告)号：US20210217455A1

公开(公告)日：2021-07-15

申请号：US16740281

申请日：2020-01-10

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Thomas H. Kinsley ,  Fuad Badrieh

IPC: G11C11/4074 ,  G06F3/06

Abstract: Methods, systems, and devices for feedback for power management of a memory die using shorting are described. A memory device may short a first rail with a voltage source for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit of a memory system. The memory device may detect a condition of one or more voltage rails for delivering power coupled with the array of memory cells. The memory device may short a first rail of the network of components for delivering power with a voltage source based on detecting the condition. In some cases, the memory device may generate a feedback signal across the first rail of the network of components for delivering power based on shorting the first rail.

公开(公告)号：US20210216130A1

公开(公告)日：2021-07-15

申请号：US16740293

申请日：2020-01-10

Applicant: Micron Technology, Inc.

Inventor： Baekkyu Choi ,  Thomas H. Kinsley ,  Fuad Badrieh

IPC: G06F1/3225

Abstract: A memory device may include a pin for communicating feedback regarding a supply voltage to a power management component, such as a power management integrated circuit (PMIC). The memory device may bias the pin to a first voltage indicating that a supply voltage is within a target range. The memory device may subsequently determine that a supply voltage is outside the target range and transition the voltage at the pin from the first voltage to a second voltage indicating that the supply voltage is outside the target range. The memory device may select the second voltage based on whether the supply voltage is above or below the target range.