公开(公告)号：US11646269B2

公开(公告)日：2023-05-09

申请号：US17243411

申请日：2021-04-28

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/538 ,  H01L25/065 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5381 ,  H01L23/5386 ,  H01L23/53228 ,  H01L25/0657

Abstract: Semiconductor devices having recessed edges with plated structures, semiconductor assemblies formed therefrom, and associated systems and methods are disclosed herein. In one embodiment, a semiconductor assembly includes a first semiconductor device and a second semiconductor device. The first semiconductor device can include an upper surface and a first dielectric layer over the upper surface, the second semiconductor device can include a lower surface and a second dielectric layer over the lower surface, and the first and second dielectric layers can be bonded to couple the first and second semiconductor devices. The first and second dielectric layers can each include a plurality of inwardly extending recesses exposing a plurality of metal structures on the respective upper and lower surfaces, and the upper surface recesses and metal structures can correspond to the lower surface recesses and metal structures. The metal structures can be electrically coupled by plated structures positioned in the recesses.

公开(公告)号：US20220352077A1

公开(公告)日：2022-11-03

申请号：US17243411

申请日：2021-04-28

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/532 ,  H01L21/768

Abstract: Semiconductor devices having recessed edges with plated structures, semiconductor assemblies formed therefrom, and associated systems and methods are disclosed herein. In one embodiment, a semiconductor assembly includes a first semiconductor device and a second semiconductor device. The first semiconductor device can include an upper surface and a first dielectric layer over the upper surface, the second semiconductor device can include a lower surface and a second dielectric layer over the lower surface, and the first and second dielectric layers can be bonded to couple the first and second semiconductor devices. The first and second dielectric layers can each include a plurality of inwardly extending recesses exposing a plurality of metal structures on the respective upper and lower surfaces, and the upper surface recesses and metal structures can correspond to the lower surface recesses and metal structures. The metal structures can be electrically coupled by plated structures positioned in the recesses.

公开(公告)号：US20220336280A1

公开(公告)日：2022-10-20

申请号：US17231313

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L21/78 ,  H01L23/544 ,  H01L21/326 ,  H01L21/67

Abstract: Microelectronic devices may include an active surface and a side surface. The side surface may include a first portion having a reflective surface and a second portion having a non-reflective surface. The reflective surface may be formed by depositing a conductive material in trenches formed in material of the wafer along streets between the microelectronic devices on a wafer. The conductive material may be heated. The wafer may be cooled after the conductive material is heated fracturing the wafer along the streets and separating the microelectronic devices.

公开(公告)号：US20220320037A1

公开(公告)日：2022-10-06

申请号：US17845635

申请日：2022-06-21

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jaekyu Song ,  Sui Chi Huang

IPC: H01L23/00 ,  H01L21/67 ,  H01L21/50

Abstract: Systems and methods for controlling contamination during thermocompression bonding are provided herein. The tool generally includes a bondhead having a first channel extending in a lateral direction from a first port along a second side toward a perimeter of the bondhead. In several examples, the bondhead includes a second channel fluidly coupled to a second port and extending in a lateral direction along an inset surface of the bondhead, where the second channel at least partially surrounds the first channel. In other examples, the tool includes a vacuum manifold having a vacuum opening positioned laterally outward from the bondhead. A first flow unit is coupled to the first channel and is configured to withdraw air. A second flow unit is coupled to the second port or the manifold to withdraw fluid and prevent outgassing bonding materials from entering the first channel, depositing on the bondhead, and/or contaminating neighboring semiconductor components.

公开(公告)号：US11410961B2

公开(公告)日：2022-08-09

申请号：US16821536

申请日：2020-03-17

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065

Abstract: This patent application relates to methods and apparatus for temperature modification within a stack of microelectronic devices for mutual collective bonding of the microelectronic devices, and to related substrates and assemblies.

公开(公告)号：US20210384042A1

公开(公告)日：2021-12-09

申请号：US16895751

申请日：2020-06-08

Applicant: Micron Technology, Inc.

Inventor： Xiaopeng Qu ,  Hyunsuk Chun ,  Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L21/447 ,  H01L21/67 ,  H01L21/033

Abstract: This patent application relates to methods and apparatus for temperature modification and reduction of contamination in bonding stacked microelectronic devices with heat applied from a bond head of a thermocompression bonding tool. The stack is substantially enclosed within a skirt carried by the bond head to reduce heat loss and contaminants from the stack, and heat may be added from the skirt.

公开(公告)号：US11024595B2

公开(公告)日：2021-06-01

申请号：US15625676

申请日：2017-06-16

Applicant: Micron Technology, Inc.

Inventor： Benjamin L. McClain ,  Brandon P. Wirz ,  Zhaohui Ma

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00

Abstract: A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.

公开(公告)号：US20210066246A1

公开(公告)日：2021-03-04

申请号：US16553504

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Bradley R. Bitz ,  Pei Sian Shao

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  B29C43/18 ,  B29C43/36

Abstract: Methods for fabricating microelectronic device assemblies, the method comprising providing mutually spaced stacks of microelectronic devices on a substrate and substantially concurrently encapsulating the stacks of microelectronic devices on the substrate and gang bonding mutually aligned conductive elements of vertically adjacent microelectronic devices. Compression molding apparatus for implementing the methods, and resulting microelectronic device assemblies are also disclosed.

公开(公告)号：US10825761B2

公开(公告)日：2020-11-03

申请号：US16200843

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Jack E. Murray

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

Abstract: An electronic device includes a substrate, a structure over the substrate having an edge wall defining at least a portion of an opening exposing a surface of the substrate, and a dielectric material adjacent and in contact with the edge wall and an adjacent portion of the surface of the substrate. The dielectric material has a profile tapering downward from adjacent the edge wall toward the substrate. Other electronic devices include a substrate and a solder mask over the substrate. The solder mask defines an opening therethrough. A supplemental mask is within the opening of the solder mask, and has a sidewall that slopes away from the solder mask. A conductive structure is adjacent and in contact with at least one of the solder mask or the supplemental mask.

公开(公告)号：US20190131272A1

公开(公告)日：2019-05-02

申请号：US15797900

申请日：2017-10-30

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Benjamin L. McClain ,  C. Alexander Ernst ,  Jeremy E. Minnich

IPC: H01L23/00

Abstract: A semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a pillar. The semiconductor device assembly includes a semiconductor device disposed over another semiconductor device. At least one pillar extends from one semiconductor device towards a pad on the other semiconductor device. The barrier on the exterior of the pillar may be a standoff to control a bond line between the semiconductor devices. The barrier may reduce solder bridging and may prevent reliability and electromigration issues that can result from the IMC formation between the solder and copper portions of a pillar. The barrier may help align the pillar with a pad when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of the semiconductor devices. Windows or slots in the barrier may permit the expansion of solder in predetermined directions while preventing bridging in other directions.