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    SELF TIMING TRAINING USING MAJORITY DECISION MECHANISM
    32.
    发明申请
    SELF TIMING TRAINING USING MAJORITY DECISION MECHANISM 有权

    公开(公告)号：US20230029528A1

    公开(公告)日：2023-02-02

    申请号：US17385340

    申请日：2021-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Takehiro Hasegawa ,  Chikara Kondo ,  Yuan He ,  Hyunui Lee

    IPC: G11C29/12 ,  G11C7/22

    Abstract: Methods for improving timing in memory devices are disclosed. A method may include sampling a data signal according to a clock signal to obtain a data sample; sampling the data signal according to an advanced clock signal to obtain an advanced data sample; and sampling the data signal according to a delayed clock signal to obtain a delayed data sample. The method may also include comparing the data sample with the advanced data sample and the delayed data sample and performing an action based on the comparison. The action may include selecting a data sample, selecting a clock signal and/or adjusting a clock signal. Associated devices and systems are also disclosed.

    APPARATUSES INCLUDING MEMORY REGIONS HAVING DIFFERENT ACCESS SPEEDS AND METHODS FOR USING THE SAME
    34.
    发明申请
    APPARATUSES INCLUDING MEMORY REGIONS HAVING DIFFERENT ACCESS SPEEDS AND METHODS FOR USING THE SAME 有权

    公开(公告)号：US20220157372A1

    公开(公告)日：2022-05-19

    申请号：US16953214

    申请日：2020-11-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yuan He ,  Daigo Toyama ,  Chikara Kondo ,  Takehiro Hasegawa

    IPC: G11C11/4097 ,  G11C11/4091

    Abstract: Apparatuses, systems, and methods for faster memory access regions. A memory array may have a fiat bank which has a greater access speed than a second bank. For example the first bank may have a reduced read latency compared to the second bank. The first bank may have structural differences, such as reduced word line and/or reduced global input output (GIO) line length. In some embodiments, the first and second bank may have separate bank pad data buses, and data terminals. In some embodiments, they may share the bank pads data bus, and data terminals. In some embodiments, when an access command is received for the first (faster) bank while an access command to the second (slower) bank is still processing, the access to the faster bank may interrupt the access to the slower bank.

    APPARATUSES AND METHODS FOR IN-LINE NO OPERATION REPEAT COMMANDS
    35.
    发明申请
    APPARATUSES AND METHODS FOR IN-LINE NO OPERATION REPEAT COMMANDS 有权

    公开(公告)号：US20210182065A1

    公开(公告)日：2021-06-17

    申请号：US16715416

    申请日：2019-12-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Chikara Kondo ,  Roman A. Royer

    IPC: G06F9/30 ,  G06F9/38 ,  G06F13/16

    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for in-line no operation (NOP) repeat commands. An algorithmic pattern generator (APG) may be loaded with a set of instructions. A line of the instructions may include an active command and an NOP repeat command. The active command may be a command to be provided by the APG when the line of instruction is executed. The NOP repeat command may be a value which indicates a number of times that an NOP command should be issued after the active command when the line of instruction is executed. The APG may include an NOP controller circuit (and/or phase controller circuit) which determines when the next active command should be provided based, in part, on a count of the number of times that an NOP command is issued.

    Apparatuses and methods for direct access hybrid testing
    36.
    发明授权
    Apparatuses and methods for direct access hybrid testing 有权

    公开(公告)号：US10896738B1

    公开(公告)日：2021-01-19

    申请号：US16590694

    申请日：2019-10-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Chiaki Dono ,  Chikara Kondo ,  Roman A. Royer

    IPC: G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/30 ,  G11C29/36 ,  G11C29/12

    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for direct access hybrid testing. A memory device, such as a high bandwidth memory (HBM) may include direct access terminals. During a testing procedure, test instructions may be provided to the memory through the direct access terminals. The test instructions include a data pointer which is associated with one of a plurality of test patterns pre-loaded in the memory and an address. The selected test pattern may be written to, and subsequently read from, the memory cells associated with the address. The read test pattern may be compared to the selected test pattern to generate result information. The test patterns may be loaded to the memory, and the result information may be read out from the memory, in an operational mode different than the operational mode in which the test instructions are provided.

    TSV redundancy and TSV test select scheme
    37.
    发明授权
    TSV redundancy and TSV test select scheme 有权

    公开(公告)号：US10468386B1

    公开(公告)日：2019-11-05

    申请号：US16183961

    申请日：2018-11-08

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Homare Sato ,  Chikara Kondo ,  Akira Ide

    IPC: H01L25/065 ,  G01R31/28

    Abstract: An apparatus including through substrate vias (TSVs) used to interconnect stacked chips is described. The apparatus according to an embodiment includes a plurality of first selection lines each extending in a first direction; a plurality of second selection lines each extending in a second direction to cross the plurality of first selection lines; and a plurality of a TSV units disposed in intersections of the plurality of first selection lines and the plurality of second selection lines, respectively. Each TSV unit of the plurality of TSV units includes a TSV; a switch coupled to the TSV; and a selection circuit. The selection circuit is configured to control a switching state of the switch responsive to each of an associated one of the plurality of first selection lines and an associated one of the plurality of second selection lines being set to an active level.

    Semiconductor layered device with data bus
    39.
    发明授权
    Semiconductor layered device with data bus 有权

    公开(公告)号：US10373657B2

    公开(公告)日：2019-08-06

    申请号：US15233821

    申请日：2016-08-10

    Applicant: Micron Technology, Inc.

    Inventor： Chikara Kondo ,  Chiaki Dono

    IPC: G11C7/10 ,  G06F13/42 ,  G11C5/02 ,  G11C5/06 ,  G11C7/22

    Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.

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