公开(公告)号：US20240168895A1

公开(公告)日：2024-05-23

申请号：US18426220

申请日：2024-01-29

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Christian M. Gyllenskog ,  David Aaron Palmer

IPC: G06F13/16 ,  G06F11/30 ,  G06F12/02 ,  G06F12/0868 ,  G06F13/24

CPC classification number: G06F13/1668 ,  G06F11/3037 ,  G06F11/3058 ,  G06F12/0238 ,  G06F12/0868 ,  G06F13/24

Abstract: Various examples are directed to devices and methods involving a host device and a memory system, the memory system comprising a memory controller and a plurality of memory locations. The memory system may send to the host device a first message describing background operations to be performed at the memory system. The memory system may receive from the host device a second message indicating permission to execute the background operations and may begin to execute at least one background operation.

公开(公告)号：US20240061767A1

公开(公告)日：2024-02-22

申请号：US17892535

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/02

CPC classification number: G06F12/023

Abstract: A system includes a memory device associated with a logical address space, and a processing device, operatively coupled to the memory device, to perform operations including providing, to a host system, usable capacity information and supported logical address granularity information for the logical address space, obtaining, from the host system, a logical address granularity configuration for a partition of the logical address space, and providing, to the host system, an acknowledgement of receipt of the logical address granularity configuration.

公开(公告)号：US20240045596A1

公开(公告)日：2024-02-08

申请号：US17881294

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Jonathan S. Parry ,  David Aaron Palmer ,  Luca Porzio ,  Giuseppe Cariello ,  Stephen Hanna

IPC: G06F3/06

CPC classification number: G06F3/0617 ,  G06F3/0653 ,  G06F3/0679

Abstract: Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

公开(公告)号：US11775422B2

公开(公告)日：2023-10-03

申请号：US17399406

申请日：2021-08-11

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  David Aaron Palmer ,  Giuseppe Cariello

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0253 ,  G06F2212/466 ,  G06F2212/7201

Abstract: Methods, systems, and devices for logic remapping techniques are described. A memory system may receive a write command to store information at a first logical address of the memory system. The memory system may generate a first entry of a logical-to-physical mapping that maps the first logical address with a first physical address that stores the information. The memory system may perform a defragmentation operation or other remapping operation. In such a defragmentation operation, the memory system may remap the first logical address to a second logical address, such that the second logical address is mapped to the first physical address. The memory system may generate a second entry of a logical-to-logical mapping that maps the first logical address with the second logical address.

公开(公告)号：US11734170B2

公开(公告)日：2023-08-22

申请号：US17679018

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/02 ,  G06F12/0873 ,  G06F12/0871

CPC classification number: G06F12/0246 ,  G06F12/0871 ,  G06F12/0873 ,  G06F2212/1052 ,  G06F2212/2022 ,  G06F2212/305 ,  G06F2212/608 ,  G06F2212/7201

Abstract: Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.

公开(公告)号：US20230236986A1

公开(公告)日：2023-07-27

申请号：US18095782

申请日：2023-01-11

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F12/0893

CPC classification number: G06F12/0893 ,  G06F2212/1044 ,  G06F2212/6012

Abstract: Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

公开(公告)号：US11693732B2

公开(公告)日：2023-07-04

申请号：US17014771

申请日：2020-09-08

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Nadav Grosz ,  Lance W. Dover ,  Yoav Weinberg

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G06F13/42 ,  G06F12/14

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/1408 ,  G06F13/4221 ,  G06F2212/7201

Abstract: A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.

公开(公告)号：US11561892B2

公开(公告)日：2023-01-24

申请号：US17118152

申请日：2020-12-10

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Deping He ,  David Aaron Palmer

IPC: G06F12/02 ,  G11C16/10 ,  G11C11/16

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a pattern of host accessing the device are discussed. The host access pattern can be represented by how frequent the device is in idle states free of active host access. An exemplary memory device includes a memory controller to track a count of idle periods during a specified time window, and to adjust an amount of memory space to be freed by a GC operation in accordance with the count of idle periods. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the count of idle periods during the specified time window.

公开(公告)号：US11537327B2

公开(公告)日：2022-12-27

申请号：US17240723

申请日：2021-04-26

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06 ,  G06F11/07 ,  G06F11/10 ,  G11C29/52

Abstract: Devices and techniques for an adjustable watchdog in a memory device are disclosed herein. A memory operation command is received at a first time with a memory device from a host. A reset signal is received, with the memory device from the host, at a second time following the first time. A time interval between the first time and the second time is measured. A delay interval for a timer in the memory device to reset the memory device independently of receiving a further reset signal from the host is established based on the measured time interval.

公开(公告)号：US20220391134A1

公开(公告)日：2022-12-08

申请号：US17338455

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

Abstract: Methods, systems, and devices for tracking data locations for improved memory performance are described. A logical address space may be partitioned into ranges of logical addresses. A group of designators may be provided for each physical partition. Each designator may correspond to a respective logical partition. The memory system may determine the logical partition associated with data written to a physical partition and set the corresponding designator, if it is not already set, in the group associated with the physical partition. Upon receipt of a command (e.g., from a host device) to perform a purge on physical partitions containing data associated with a particular logical partition, the memory system may determine the affected physical partitions based on the designator corresponding to the logical partition being set in the respective groups and may perform the selective purge on those physical partitions.