公开(公告)号：US20220124051A1

公开(公告)日：2022-04-21

申请号：US17074988

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer ,  Kirk D. Pospesel ,  Michael Grassi

IPC: H04L12/937 ,  H04L12/863 ,  H04L12/805 ,  H04L12/931

Abstract: Devices and techniques for packet arbitration for buffered packets in a network device are described herein. A packet can be received at an input of the network device. The packet can be placed in a buffer for the input and a characteristic of the packet can be obtained. A record for the packet, that includes the characteristic, is written into a data structure that is independent of the buffer. Arbitration, based on the characteristic of the packet in the record, can then be performed among multiple packets to select a next packet from the buffer for delivery to an output.

公开(公告)号：US20240170453A1

公开(公告)日：2024-05-23

申请号：US17075117

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Michael G. Placke ,  Tony Brewer

IPC: G06F13/20

CPC classification number: G06F13/20 ,  G06F2213/40

Abstract: A chiplet-based system comprises a substrate including conductive interconnect and multiple chiplets arranged on the interposer and interconnected using the conductive interconnect of the substrate. A chiplet includes multiple columns of multiple input-output (I/O) channels and the I/O channels are connected to a block of I/O pads and each side of the chiplet includes multiple blocks of the I/O pads. The multiple blocks of I/O pads on the side of the chiplet are arranged symmetrically relative to a centerline of the chiplet and each block of I/O pads on the side of the chiplet is at a common distance from any adjacent block of I/O pads on the side.

公开(公告)号：US11985078B2

公开(公告)日：2024-05-14

申请号：US17897557

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer ,  Kirk D. Pospesel ,  Michael Grassi

IPC: H04L49/25 ,  H04L47/36 ,  H04L47/62 ,  H04L49/253 ,  H04L49/35

CPC classification number: H04L49/254 ,  H04L47/36 ,  H04L47/6225 ,  H04L49/35

Abstract: Devices and techniques for packet arbitration for buffered packets in a network device are described herein. A packet can be received at an input of the network device. The packet can be placed in a buffer for the input and a characteristic of the packet can be obtained. A record for the packet, that includes the characteristic, is written into a data structure that is independent of the buffer. Arbitration, based on the characteristic of the packet in the record, can then be performed among multiple packets to select a next packet from the buffer for delivery to an output.

公开(公告)号：US11935600B2

公开(公告)日：2024-03-19

申请号：US18117900

申请日：2023-03-06

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F13/16 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/102 ,  G06F9/526 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/1605 ,  G06F13/1668 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3459 ,  G06F2212/1024

Abstract: Devices and techniques for programmable atomic operator resource locking are described herein. A request for a programmable atomic operator (PAO) can be received at a memory controller that includes a programmable atomic unit (PAU). Here, the request includes an identifier for the PAO and a memory address. The memory addressed is processed to identify a lock value. A verification can be performed to determine that the lock value indicates that there is no lock corresponding to the memory address. Then, the lock value is set to indicate that there is now a lock corresponding to the memory address and the PAO is invoked based on the identifier for the PAO. In response to completion of the PAO, the lock value is set to indicate that there is no longer a lock corresponding to the memory address.

公开(公告)号：US11831543B2

公开(公告)日：2023-11-28

申请号：US17744158

申请日：2022-05-13

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: H04L45/586 ,  H04L45/74 ,  H04L49/00 ,  H04L45/00 ,  H04L69/22

CPC classification number: H04L45/38 ,  H04L45/586 ,  H04L45/74 ,  H04L49/3072 ,  H04L69/22

Abstract: Implementations of the present disclosure are directed to systems and methods for flow control using a multiple flit interface. A credit return field is used in a credit-based flow control system to indicate that one or more credits are being returned to a sending device from a receiving device. Based on the number of credits available, the sending device determines whether to send device or wait until more credits are returned. The amount of buffer space used by the receiver to store the packet is determined by the number of transfer cycles used to receive the packet, not the number of flits comprising the packet. This is enabled by having the buffer be as wide as the bus. The receiver returns credits to the sender based on the number of buffer rows used to store the received packet, not the number of flits comprising the packet.

公开(公告)号：US11829323B2

公开(公告)日：2023-11-28

申请号：US17901480

申请日：2022-09-01

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F15/82 ,  G06F9/4401

CPC classification number: G06F15/82 ,  G06F9/4406

Abstract: Disclosed in some examples, are methods, systems, programmable atomic units, and machine-readable mediums that provide an exception as a response to the calling processor. That is, the programmable atomic unit will send a response to the calling processor. The calling processor will recognize that the exception has been raised and will handle the exception. Because the calling processor knows which process triggered the exception, the calling processor (e.g., the Operating System) can take appropriate action, such as terminating the calling process. The calling processor may be a same processor as that executing the programmable atomic transaction, or a different processor (e.g., on a different chiplet).

公开(公告)号：US11693690B2

公开(公告)日：2023-07-04

申请号：US17074770

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/52 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F9/466 ,  G06F9/3004 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/524 ,  G06F12/0246 ,  G06F13/1668

Abstract: Disclosed is an instruction for a programmable atomic transaction that is executed as the last instruction and that terminates the executing thread, waits for all outstanding store operations to finish, clears the programmable atomic lock, and sends a completion response back to the issuing process. This guarantees that the programmable atomic lock is cleared when the transaction completes. By coupling thread termination with clearing the lock bit, this guarantees that the thread cannot terminate without clearing the lock.

公开(公告)号：US20230205524A1

公开(公告)日：2023-06-29

申请号：US18111744

申请日：2023-02-20

Applicant: Micron Technology , Inc.

Inventor： Tony Brewer

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/46 ,  G06F12/0815 ,  G06F12/0875 ,  G06F15/78

CPC classification number: G06F9/3004 ,  G06F9/325 ,  G06F9/466 ,  G06F12/0815 ,  G06F12/0875 ,  G06F15/781

Abstract: Disclosed in some examples are systems, methods, devices, and machine-readable mediums to detect and terminate programmable atomic transactions that are stuck in an infinite loop. In order to detect and terminate these transactions, the programmable atomic unit may use an instruction counter that increments each time an instruction is executed during execution of a programmable atomic transaction. If the instruction counter meets or exceeds a threshold instruction execution limit without reaching the termination instruction, the programmable atomic transaction may be terminated, all resources used (e.g., memory locks) may be freed, and a response may be sent to a calling processor.

公开(公告)号：US20230195348A1

公开(公告)日：2023-06-22

申请号：US17870254

申请日：2022-07-21

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F3/0644 ,  G06F13/1668 ,  G06F3/061 ,  G06F12/0253 ,  G06F3/0679 ,  G06F2212/7205 ,  G06F2213/16

Abstract: Disclosed in some examples, are methods, systems, devices, and machine readable mediums that store instructions for programmable atomic transactions in a memory of the programmable atomic unit prior to execution of the programmable atomic transaction. The memory in some examples may be an instruction RAM. The memory in some examples may be partitioned into partitions of a fixed size that stores a same number of instructions. Each programmable atomic transaction may use one or more contiguously located instruction partitions. By loading the instructions ahead of time, the instructions are ready for execution when the transaction is requested.

公开(公告)号：US11614891B2

公开(公告)日：2023-03-28

申请号：US17074937

申请日：2020-10-20

Applicant: Micron Technology, Inc.

Inventor： Tony Brewer

IPC: G06F3/06

Abstract: Devices and techniques for communicating a programmable atomic operator to a memory controller are described herein. A memory controller can receive a memory request and extract a command indicator that indicates a programmable atomic operator (PAO) command from the memory request. The memory controller can then extract a PAO index from the request and invoke the PAO based on the PAO index.