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    Methods, apparatuses, and circuits for bimodal disable circuits
    32.
    发明授权
    Methods, apparatuses, and circuits for bimodal disable circuits 有权
    双模禁用电路的方法，装置和电路

    公开(公告)号：US08692603B2

    公开(公告)日：2014-04-08

    申请号：US13975100

    申请日：2013-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Eric Booth ,  Tyler J. Gomm ,  Kallol Mazumder ,  Scott E. Smith ,  John F. Schreck

    IPC: H03K3/00

    CPC classification number: H03L1/00 ,  G06F1/10 ,  H03K5/132 ,  H03K5/133 ,  H03K21/38

    Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

    Abstract translation: 公开了用于双模禁止电路的电路，集成电路和方法。 在一个这样的示例性方法中，维持计数器，其中计数器指示在多个禁用周期中的至少一个的至少一部分期间输出信号将被禁用的逻辑电平。 由计数器指示的逻辑电平转换。 响应于指示输出信号被使能的使能信号，输出信号被提供作为输出信号，并且输出信号在由计数器指示的逻辑电平处被禁用，响应于使能信号，指示输出信号为 被禁用

    Devices including phase inverters and phase mixers
    33.
    发明授权
    Devices including phase inverters and phase mixers 有权
    设备包括相位逆变器和相位混合器

    公开(公告)号：US08624644B2

    公开(公告)日：2014-01-07

    申请号：US13957333

    申请日：2013-08-01

    Applicant: Micron Technology, Inc.

    Inventor： Tyler J. Gomm

    IPC: H03L7/06

    CPC classification number: H03L7/0818 ,  H03K5/133 ,  H03K5/14 ,  H03L7/0814 ,  H03L7/089

    Abstract: Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.

    Abstract translation: 公开了锁定环路，延迟线路，延迟电路和用于延迟信号的方法。 示例延迟电路包括包括多个延迟级的延迟线，每个延迟级具有输入并且还具有单个反相延迟器件，并且还包括耦合到延迟线的两相出口树，并且被配置为提供第一和 第二输出时钟信号响应于来自多个延迟级的延迟级的输入的时钟信号。 另一示例延迟电路包括被配置为提供多个延迟的时钟信号的延迟线，每个延迟的时钟信号相对于等于单个反相延迟器件的延迟的先前延迟的时钟信号具有延迟。 示例延迟电路还包括被配置为响应延迟的时钟信号提供第一和第二输出时钟信号的两相出口树。

    METHODS, APPARATUSES, AND CIRCUITS FOR BIMODAL DISABLE CIRCUITS
    34.
    发明申请
    METHODS, APPARATUSES, AND CIRCUITS FOR BIMODAL DISABLE CIRCUITS 有权
    双向禁用电路的方法，装置和电路

    公开(公告)号：US20140002148A1

    公开(公告)日：2014-01-02

    申请号：US13975100

    申请日：2013-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Eric Booth ,  Tyler J. Gomm ,  Kallol Mazumder ,  Scott E. Smith ,  John F. Schreck

    IPC: H03L1/00

    CPC classification number: H03L1/00 ,  G06F1/10 ,  H03K5/132 ,  H03K5/133 ,  H03K21/38

    Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

    Abstract translation: 公开了用于双模禁止电路的电路，集成电路和方法。 在一个这样的示例性方法中，维持计数器，其中计数器指示在多个禁用周期中的至少一个的至少一部分期间输出信号将被禁用的逻辑电平。 由计数器指示的逻辑电平转换。 响应于指示输出信号被使能的使能信号，输出信号被提供作为输出信号，并且输出信号在由计数器指示的逻辑电平处被禁用，响应于使能信号，指示输出信号为 被禁用

    MEMORY DEVICE WITH 4N AND 8N DIE STACKS
    35.
    发明公开
    MEMORY DEVICE WITH 4N AND 8N DIE STACKS 审中-公开

    公开(公告)号：US20240281390A1

    公开(公告)日：2024-08-22

    申请号：US18410808

    申请日：2024-01-11

    Applicant: Micron Technology, Inc.

    Inventor： Dong Uk Lee ,  Sujeet Ayyapureddi ,  Lingming Yang ,  Tyler J. Gomm

    IPC: G06F13/16

    CPC classification number: G06F13/1678 ,  G06F13/161 ,  G06F13/1694

    Abstract: A memory device includes a stack of eight memory dies having an 8N architecture and a stack of four memory dies having a 4N architecture. A first half and a second half of the stack of eight memory dies can each include 32 channels divided equally across the first half of dies and across the second half of dies. Banks of each of the 32 channels on the first half of dies can be associated with respective first pseudo channels. Banks of each of the 32 channels on the second half of dies can be associated with respective second pseudo channels. The stack of four memory dies can include the 32 channels divided equally amongst the dies, and the banks of each of the 32 channels on the stack of four memory dies can be divided equally across the respective first and second pseudo channels.

    SYSTEMS AND TECHNIQUES FOR JITTER REDUCTION
    36.
    发明公开
    SYSTEMS AND TECHNIQUES FOR JITTER REDUCTION 审中-公开

    公开(公告)号：US20240007092A1

    公开(公告)日：2024-01-04

    申请号：US17852657

    申请日：2022-06-29

    Applicant: Micron Technology, Inc.

    Inventor： Eric J. Stave ,  Tyler J. Gomm

    IPC: H03K5/156 ,  G11C7/22 ,  H03K19/21 ,  H03K5/1534

    CPC classification number: H03K5/1565 ,  G11C7/222 ,  H03K19/21 ,  H03K5/1534

    Abstract: A device includes a clock input circuit that when in operation receives a clock signal and transmits an internal clock signal based on the clock signal. The device also includes an internal clock generator coupled to the clock input circuit to receive the internal clock signal, wherein the internal clock generator comprises clock adjustment circuitry that when in operation generates a phase controlled internal clock signal having subsequent clock edges based upon a single clock edge of the internal clock signal, wherein the phase controlled internal clock signal comprises a first frequency as a multiple of a second frequency of the internal clock signal.

    Deterministic Jitter Generator with Controllable Probability Distribution
    39.
    发明申请
    Deterministic Jitter Generator with Controllable Probability Distribution 有权

    公开(公告)号：US20220294428A1

    公开(公告)日：2022-09-15

    申请号：US17198925

    申请日：2021-03-11

    Applicant: Micron Technology, Inc.

    Inventor： Tyler J. Gomm

    IPC: H03K3/017 ,  H03K3/037 ,  H03K19/20 ,  H03K3/84 ,  H03K5/01 ,  G06F1/10

    Abstract: A jitter generator may include a duty cycle code generator that generates a duty cycle control signal and an input buffer that outputs a signal based on its duty cycle. The input buffer may be coupled to the duty cycle code generator and to a source of a clock signal. After receiving the clock signal, the input buffer outputs the clock signal having jitter relative to the clock signal received from the source. The jitter may be added at least in part by components of the input buffer offsetting different transitions of the clock signal according to the duty cycle. Jitter may be added when the duty cycle changes in response to changes in the duty cycle control signal, such as in response to number generator circuitry of the duty cycle code generator update its output number, in response to a mode change received from a controller, or the like.

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