公开(公告)号：US11121144B2

公开(公告)日：2021-09-14

申请号：US16682544

申请日：2019-11-13

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  David Daycock ,  Subramanian Krishnan ,  Leroy Ekarista Wibowo

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11519

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. First insulator material is above the stack. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in and upwardly project from an uppermost material that is directly above the stack. Conducting material is directly against laterally-inner sides of individual of the upwardly-projecting channel-material strings and project upwardly from the individual upwardly-projecting channel-material strings. A ring comprising insulating material is formed individually circumferentially about the upwardly-projecting conducting material. Second insulator material is formed above the first insulator material, the ring, and the upwardly-projecting conducting material. The first and second insulator materials comprise different compositions relative one another. Conductive vias are formed in the second insulator material that are individually directly electrically coupled to the individual channel-material strings through the upwardly-projecting conducting material. Other embodiments, including structure, are disclosed.

公开(公告)号：US20210257385A1

公开(公告)日：2021-08-19

申请号：US17215308

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/3213 ,  H01L27/11556

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US20210143164A1

公开(公告)日：2021-05-13

申请号：US16682544

申请日：2019-11-13

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  David Daycock ,  Subramanian Krishnan ,  Leroy Ekarista Wibowo

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/3213

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. First insulator material is above the stack. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in and upwardly project from an uppermost material that is directly above the stack. Conducting material is directly against laterally-inner sides of individual of the upwardly-projecting channel-material strings and project upwardly from the individual upwardly-projecting channel-material strings. A ring comprising insulating material is formed individually circumferentially about the upwardly-projecting conducting material. Second insulator material is formed above the first insulator material, the ring, and the upwardly-projecting conducting material. The first and second insulator materials comprise different compositions relative one another. Conductive vias are formed in the second insulator material that are individually directly electrically coupled to the individual channel-material strings through the upwardly-projecting conducting material. Other embodiments, including structure, are disclosed.

公开(公告)号：US20210143054A1

公开(公告)日：2021-05-13

申请号：US16682349

申请日：2019-11-13

Applicant: Micron Technology, Inc.

Inventor： Lingyu Kong ,  David Daycock ,  Venkata Satyanarayana Murthy Kurapati ,  Leroy Ekarista Wibowo

IPC: H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. A first insulator tier is above the stack. First insulator material of the first insulator tier comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in the stack and in the first insulator tier. Conducting material is in the first insulator tier directly against sides of individual of the channel-material strings. A second insulator tier is formed above the first insulator tier and the conducting material. Second insulator material of the second insulator tier comprises at least one of the (a) and the (b). Conductive vias are formed and extend through the second insulator tier and that are individually directly electrically coupled to the individual channel-material strings through the conducting material. Other aspects, including structure independent of method, are disclosed.

公开(公告)号：US10998336B2

公开(公告)日：2021-05-04

申请号：US16573218

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock

IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

Abstract: Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge-blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.

公开(公告)号：US20200350333A1

公开(公告)日：2020-11-05

申请号：US16933693

申请日：2020-07-20

Applicant: Micron Technology, Inc.

Inventor： Liu Liu ,  David Daycock ,  Rithu K. Bhonsle ,  Giovanni Mazzone ,  Narula Bilik ,  Jordan D. Greenlee ,  Minsoo Lee ,  Benben Li

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L21/32 ,  H01L27/1157 ,  H01L21/311 ,  H01L27/11556

Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.

公开(公告)号：US10734395B2

公开(公告)日：2020-08-04

申请号：US16663068

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11551 ,  H01L27/11553

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10541252B2

公开(公告)日：2020-01-21

申请号：US16410973

申请日：2019-05-13

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/423 ,  H01L21/28 ,  H01L29/10 ,  H01L29/792

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20180286883A1

公开(公告)日：2018-10-04

申请号：US15997992

申请日：2018-06-05

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock

IPC: H01L27/11582 ,  H01L29/423 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66

Abstract: Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge-blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.

公开(公告)号：US10038008B1

公开(公告)日：2018-07-31

申请号：US15419813

申请日：2017-01-30

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  David Daycock

IPC: H01L29/792 ,  H01L27/11582 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

Abstract: Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge-blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.