公开(公告)号：US11805645B2

公开(公告)日：2023-10-31

申请号：US16542645

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Nicholas R. Tapias ,  Andrew Li ,  Adam W. Saxler ,  Kunal Shrotri ,  Erik R. Byers ,  Matthew J. King ,  Diem Thy N. Tran ,  Wei Yeeng Ng ,  Anish A. Khandekar

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/285 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02631 ,  H01L21/02636 ,  H01L21/28568 ,  H10B41/27

Abstract: Some embodiments include a structure having an opening extending into an integrated configuration. A first material is within the opening, and is configured to create an undulating topography relative to a sidewall of the opening. The undulating topography has a surface roughness characterized by a mean roughness parameter Rmean which is the mean peak-to-valley distance along the undulating topography. The Rmean is at least about 4 nm. A second material is within the opening and along at least a portion of the undulating topography. The first and second materials are compositionally different from one another. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11751393B2

公开(公告)日：2023-09-05

申请号：US17524987

申请日：2021-11-12

Applicant: Micron Technology, Inc.

Inventor： Manzar Siddik ,  Chris M. Carlson ,  Terry H. Kim ,  Kunal Shrotri ,  Srinath Venkatesan

IPC: H01L27/11582 ,  H10B43/27 ,  H01L21/3215 ,  H01L21/3115 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/3115 ,  H01L21/3215 ,  H10B41/27

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.

公开(公告)号：US20230061820A1

公开(公告)日：2023-03-02

申请号：US18047214

申请日：2022-10-17

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Kunal Shrotri

IPC: H01L27/11556 ,  H01L27/11585

Abstract: A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.

公开(公告)号：US20220077186A1

公开(公告)日：2022-03-10

申请号：US17524987

申请日：2021-11-12

Applicant: Micron Technology, Inc.

Inventor： Manzar Siddik ,  Chris M. Carlson ,  Terry H. Kim ,  Kunal Shrotri ,  Srinath Venkatesan

IPC: H01L27/11582 ,  H01L21/3215 ,  H01L21/3115 ,  H01L27/11556

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.

公开(公告)号：US11195854B2

公开(公告)日：2021-12-07

申请号：US16783981

申请日：2020-02-06

Applicant: Micron Technology, Inc.

Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

公开(公告)号：US20210375898A1

公开(公告)日：2021-12-02

申请号：US16887178

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Kunal Shrotri

IPC: H01L27/11556 ,  H01L27/11585

Abstract: A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.

公开(公告)号：US20200251347A1

公开(公告)日：2020-08-06

申请号：US16854283

申请日：2020-04-21

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Gordon A. Haller ,  Tom J. John ,  Anish A. Khandekar ,  Christopher Larsen ,  Kunal Shrotri

IPC: H01L21/311 ,  H01L27/11582 ,  H01L21/02 ,  H01L27/11556

Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.

公开(公告)号：US20200052134A1

公开(公告)日：2020-02-13

申请号：US16659478

申请日：2019-10-21

Applicant: Micron Technology, Inc.

Inventor： Fei Wang ,  Kunal Shrotri ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Duo Mao ,  Zhixin Xu ,  Ee Ee Eng ,  Jie Li ,  Dong Liang

IPC: H01L29/792 ,  G11C16/04 ,  G11C16/08 ,  H01L27/1157 ,  H01L29/66 ,  H01L21/28

Abstract: A method of forming Si3Nx, where “x” is less than 4 and at least 3, comprises decomposing a Si-comprising precursor molecule into at least two decomposition species that are different from one another, at least one of the at least two different decomposition species comprising Si. An outer substrate surface is contacted with the at least two decomposition species. At least one of the decomposition species that comprises Si attaches to the outer substrate surface to comprise an attached species. The attached species is contacted with a N-comprising precursor that reacts with the attached species to form a reaction product comprising Si3Nx, where “x” is less than 4 and at least 3. Other embodiments are disclosed, including constructions made in accordance with method embodiments of the invention and constructions independent of method of manufacture.

公开(公告)号：US10388665B1

公开(公告)日：2019-08-20

申请号：US15992959

申请日：2018-05-30

Applicant: Micron Technology, Inc.

Inventor： Zhiqiang Xie ,  Chris M. Carlson ,  Justin B. Dorhout ,  Anish A. Khandekar ,  Greg Light ,  Ryan Meyer ,  Kunal R. Parekh ,  Dimitrios Pavlopoulos ,  Kunal Shrotri

IPC: H01L27/11582 ,  H01L21/02 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/311

Abstract: An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers have terminal ends corresponding to control-gate regions of individual memory cells. The control-gate regions individually comprise part of a wordline in individual of the wordline tiers. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions. Charge-storage material of the individual memory cells extends elevationally along individual of the charge-blocking regions. Channel material extends elevationally along the vertical stack. Insulative charge-passage material is laterally between the channel material and the charge-storage material. Elevationally-extending walls laterally separate immediately-laterally-adjacent of the wordlines. The walls comprise laterally-outer insulative material and silicon-containing material spanning laterally between the laterally-outer insulative material. The silicon-containing material comprises at least 30 atomic percent of at least one of elemental-form silicon or a silicon-containing alloy. Other aspects, including method, are also disclosed.

公开(公告)号：US10381367B2

公开(公告)日：2019-08-13

申请号：US16002075

申请日：2018-06-07

Applicant: Micron Technology, Inc.

Inventor： Dimitrios Pavlopoulos ,  Kunal Shrotri ,  Anish A. Khandekar

IPC: H01L27/11568 ,  H01L27/1157 ,  H01L29/66 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/792 ,  H01L27/11556 ,  H01L27/11521 ,  H01L27/11519 ,  H01L29/788

Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.