公开(公告)号：US20120246448A1

公开(公告)日：2012-09-27

申请号：US13428452

申请日：2012-03-23

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/312

CPC classification number: G06F9/3836 ,  G06F9/30043 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3889 ,  G06F9/5027 ,  G06F12/0875 ,  G06F2209/507 ,  G06F2212/452 ,  Y02D10/22

Abstract: A system for executing instructions using a plurality of memory fragments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality memory fragments are coupled to the partitionable engines for providing data storage.

Abstract translation: 一种用于使用用于处理器的多个存储器片段来执行指令的系统。 该系统包括用于接收输入指令序列的全局前端调度器，其中全局前端调度器将输入指令序列划分为指令的多个代码块，并且生成描述代码块指令之间相互依赖关系的多个继承向量。 该系统还包括处理器的多个虚拟核心，其耦合以接收由全局前端调度器分配的代码块，其中每个虚拟核心包括多个可分区引擎的相应资源子集，其中通过使用 根据虚拟核心模式并根据各自的继承向量的可分割引擎。 多个存储器片段耦合到可分割引擎以提供数据存储。

公开(公告)号：US20120198157A1

公开(公告)日：2012-08-02

申请号：US13359767

申请日：2012-01-27

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F12/08

CPC classification number: G06F9/30174 ,  G06F8/52 ,  G06F9/30058 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3808 ,  G06F12/0875 ,  G06F2212/151 ,  G06F2212/452

Abstract: A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions, and assembling the plurality of guest instructions into a guest instruction block. The guest instruction block is converted into a corresponding native conversion block. The native conversion block is stored into a native cache. A mapping of the guest instruction block to corresponding native conversion block is stored in a conversion look aside buffer. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates whether the guest instruction has a corresponding converted native instruction in the native cache. The converted native instruction is forwarded for execution in response to the hit.

Abstract translation: 一种用于翻译处理器的指令的方法。 该方法包括：访问包含多个客户分支指令的多个访客指令，以及将多个访客指令组装成访客指令块。 客户指令块被转换为相应的本机转换块。 原生转换块被存储到本机高速缓存中。 访客指令块到对应的本机转换块的映射被存储在转换后备缓冲器中。 在对客户指令的后续请求之后，转换看起来缓冲器被索引以确定是否发生命中，其中该映射指示访客指令是否具有本地高速缓存中的对应转换的本机指令。 转换的本地指令被转发以执行命令。

公开(公告)号：US07761694B2

公开(公告)日：2010-07-20

申请号：US11478884

申请日：2006-06-30

Applicant: Mohammad Abdallah ,  Hon Shing Lau ,  Shou-Wen Fu ,  Aviel Timor ,  Tal Gat

Inventor： Mohammad Abdallah ,  Hon Shing Lau ,  Shou-Wen Fu ,  Aviel Timor ,  Tal Gat

IPC: G06F7/38 ,  G06F7/00

CPC classification number: G06F9/30032 ,  G06F9/30036

Abstract: In one embodiment, the present invention includes a method for receiving first and second data operands in a common execution unit and manipulating the operands responsive to an instruction to generate an output according to local control signals of a local controller of the execution unit. Various instruction types such as shuffle and shift operations may be performed in the common execution unit in a single cycle. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在公共执行单元中接收第一和第二数据操作数的方法，并且响应于根据执行单元的本地控制器的本地控制信号产生输出的指令操纵操作数。 可以在单个周期中在公共执行单元中执行诸如随机播放和移位操作的各种指令类型。 描述和要求保护其他实施例。

公开(公告)号：US20060265161A1

公开(公告)日：2006-11-23

申请号：US11124553

申请日：2005-05-06

Applicant: Bruce Querbach ,  Mohammad Abdallah ,  Amjad Khan ,  Mir Hossain ,  Sanjib Sarkar

Inventor： Bruce Querbach ,  Mohammad Abdallah ,  Amjad Khan ,  Mir Hossain ,  Sanjib Sarkar

IPC: G06F19/00

CPC classification number: G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037

Abstract: A technique includes in response to a training mode, communicating between a device and a processor of a computer system over a data bit line of a bus. The technique includes based on the communication, regulating a timing between a strobe signal and a signal that propagates over the data bit line.

公开(公告)号：US06307553B1

公开(公告)日：2001-10-23

申请号：US09053001

申请日：1998-03-31

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06T100

CPC classification number: G06F9/30032 ,  G06F9/30025 ,  G06F9/30036

Abstract: An apparatus and method for performing a MOVHPS-MOVLPS operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having a pair of data elements is accessed. A second packed data operand having two pairs of data elements is then accessed. One of the two pairs of data elements in the second packed data operand is replaced with the pair of data elements in the first packed data operand.

Abstract translation: 描述了使用计算机实现的步骤对打包数据执行MOVHPS-MOVLPS操作的装置和方法。 在一个实施例中，访问具有一对数据元素的第一打包数据操作数。 然后访问具有两对数据元素的第二打包数据操作数。 第二打包数据操作数中的两对数据元素之一被替换为第一打包数据操作数中的一对数据元素。

公开(公告)号：US09940134B2

公开(公告)日：2018-04-10

申请号：US13475708

申请日：2012-05-18

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F9/3005 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/5005 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/4068

Abstract: A method for decentralized resource allocation in an integrated circuit. The method includes receiving a plurality of requests from a plurality of resource consumers of a plurality of partitionable engines to access a plurality resources, wherein the resources are spread across the plurality of engines and are accessed via a global interconnect structure. At each resource, a number of requests for access to said each resource are added. At said each resource, the number of requests are compared against a threshold limiter. At said each resource, a subsequent request that is received that exceeds the threshold limiter is canceled. Subsequently, requests that are not canceled within a current clock cycle are implemented.

公开(公告)号：US09733942B2

公开(公告)日：2017-08-15

申请号：US13360024

申请日：2012-01-27

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/455 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30174 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30098 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/3867 ,  G06F9/3879 ,  G06F9/45516 ,  G06F12/0875 ,  G06F15/8007 ,  G06F2212/452

Abstract: A hardware based translation accelerator. The hardware includes a guest fetch logic component for accessing guest instructions; a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling guest instructions into a guest instruction block; and conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. The hardware further includes a native cache coupled to the conversion tables for storing the corresponding native conversion block, and a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block, wherein upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache.

公开(公告)号：US09710399B2

公开(公告)日：2017-07-18

申请号：US13561491

申请日：2012-07-30

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/12 ,  G06F12/126 ,  G06F12/0802

CPC classification number: G06F12/128 ,  G06F12/0802 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/126 ,  G06F2212/283 ,  G06F2212/608 ,  G06F2212/70

Abstract: Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache.

公开(公告)号：US09430410B2

公开(公告)日：2016-08-30

申请号：US13561528

申请日：2012-07-30

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/08 ,  G06F12/14

CPC classification number: G06F12/1458 ,  G06F12/0846 ,  G06F12/0897 ,  G06F2212/1052 ,  G06F2212/221 ,  G06F2212/62

Abstract: A method for supporting a plurality of load accesses is disclosed. A plurality of requests to access a data cache is accessed, and in response, a tag memory is accessed that maintains a plurality of copies of tags for each entry in the data cache. Tags are identified that correspond to individual requests. The data cache is accessed based on the tags that correspond to the individual requests. A plurality of requests to access the same block of the plurality of blocks causes an access arbitration that is executed in the same clock cycle as is the access of the tag memory.

Abstract translation: 公开了一种用于支持多个负载访问的方法。 访问多个访问数据高速缓存的请求，并且作为响应，访问维护数据高速缓存中的每个条目的标签的多个副本的标签存储器。 识别符合个别请求的标签。 基于与各个请求对应的标签访问数据高速缓存。 多个访问多个块的相同块的请求导致在与标签存储器的访问相同的时钟周期中执行的访问仲裁。

公开(公告)号：US20140189311A1

公开(公告)日：2014-07-03

申请号：US13732243

申请日：2012-12-31

Applicant: Patrice Roussel ,  Srinivas Chennupaty ,  Michael Cranford ,  Mohammad Abdallah ,  James Coke ,  Katherine Kong

Inventor： Patrice Roussel ,  Srinivas Chennupaty ,  Michael Cranford ,  Mohammad Abdallah ,  James Coke ,  Katherine Kong

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30032

Abstract: An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.

Abstract translation: 描述了使用计算机实现的步骤对打包数据执行洗牌操作的装置和方法。 在一个实施例中，访问具有至少两个数据元素的第一打包数据操作数。 具有至少两个数据元素的第二压缩数据操作数被访问。 第一打包数据操作数中的数据元素之一被混洗到目的地寄存器的较低目的地字段中，并且第二打包数据操作数中的数据元素中的一个被混洗到目的地寄存器的上目的地字段中。