公开(公告)号：US12016181B2

公开(公告)日：2024-06-18

申请号：US17665560

申请日：2022-02-06

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H10B43/27 ,  H01L23/528 ,  H01L27/02 ,  H01L29/167 ,  H01L29/47 ,  H01L29/78 ,  H01L29/792 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B53/20

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L27/0207 ,  H01L29/167 ,  H01L29/47 ,  H01L29/7827 ,  H01L29/792 ,  H10B43/10 ,  H10B43/20 ,  H10B41/10 ,  H10B41/20 ,  H10B53/20

Abstract: A 3D device, the device including: a first level including logic circuits; a second level including a plurality of memory circuits, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonds, and where the first level includes at least one voltage regulator circuit.

公开(公告)号：US11991884B1

公开(公告)日：2024-05-21

申请号：US18515255

申请日：2023-11-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H10B43/27 ,  H01L23/528 ,  H01L27/02 ,  H01L29/167 ,  H01L29/47 ,  H01L29/78 ,  H01L29/792 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B53/20

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L27/0207 ,  H01L29/167 ,  H01L29/47 ,  H01L29/7827 ,  H01L29/792 ,  H10B43/10 ,  H10B43/20 ,  H10B41/10 ,  H10B41/20 ,  H10B53/20

Abstract: A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit which includes a plurality of first transistors; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors which include a metal gate are disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; and a memory array including word-lines, the memory array includes at least four memory mini arrays, each including at least four rows by at least four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, the memory control circuit includes at least one digital to analog converter circuit.

公开(公告)号：US20240121968A1

公开(公告)日：2024-04-11

申请号：US18389769

申请日：2023-12-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist ,  Eli Lusky

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A 3D semiconductor device including: a first level including a single crystal layer, and a memory control circuit which includes at least one temperature sensor circuit and first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors—which may include a metal gate—disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; a memory array including word-lines and at least four memory mini arrays (each mini array includes at least four rows by four columns of memory cells), each memory cell includes at least one second transistor or at least one third transistor; and a connection path from fourth metal to third metal, the path includes a via disposed through the memory array.

公开(公告)号：US11956952B2

公开(公告)日：2024-04-09

申请号：US15243941

申请日：2016-08-22

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han

IPC: H10B43/20 ,  H01L27/102 ,  H10B12/00 ,  H10B41/20 ,  H10B41/50 ,  H10B43/50

CPC classification number: H10B43/20 ,  H01L27/1027 ,  H10B12/20 ,  H10B41/20 ,  H10B41/50 ,  H10B43/50

Abstract: A device, including: a first structure including first memory cells, the first memory cells including first transistors; and a second structure including second memory cells, the second memory cells including second transistors, where the second transistors overlay the first transistors, and a plurality of memory cells control lines, where the first transistors are self-aligned to the second transistors, where a second transistor channel of the second transistors is aligned to a first transistor channel of the first transistors, the aligned is at an atomic level as would have been resulted from an epitaxial growth process.

公开(公告)号：US20240065005A1

公开(公告)日：2024-02-22

申请号：US18384304

申请日：2023-10-26

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: H10B80/00 ,  H10B43/27 ,  H10B43/30 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H10B80/00 ,  H10B43/27 ,  H10B43/30 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, where the channel is horizontally-oriented and a plurality are connected to a body pillar, where the body pillar is at least temporary connected to a negative bias, the at least one memory transistor is self-aligned to an overlaying another memory transistor, both being processed following a same lithography step; a control level including a memory controller circuit and is hybrid bonded to the first structure.

公开(公告)号：US20230413586A1

公开(公告)日：2023-12-21

申请号：US18241954

申请日：2023-09-04

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H10B80/00 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H10B80/00 ,  H01L25/18 ,  H01L24/08 ,  H01L24/06 ,  H01L24/05 ,  H01L25/50 ,  H01L2224/05647 ,  H01L2224/05624 ,  H01L2224/08145 ,  H01L2224/06131 ,  H01L24/80 ,  H01L2224/80896

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors, the second level overlaying the first level; and at least four electronic circuit units (ECUs), where each of the ECUs include a first circuit, the first circuit including a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

公开(公告)号：US20230402098A1

公开(公告)日：2023-12-14

申请号：US18239117

申请日：2023-08-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: G11C16/04 ,  G11C11/408 ,  G11C16/08 ,  H10B80/00 ,  H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B12/00

CPC classification number: G11C16/0483 ,  G11C11/4087 ,  G11C16/08 ,  H10B80/00 ,  H10B43/35 ,  H10B43/10 ,  H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B12/30

Abstract: A semiconductor device, the device including: a first level including a plurality of first memory arrays, where the first level includes a plurality of first transistors and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, and where the third level includes a plurality of decoder circuits.

公开(公告)号：US20230189538A1

公开(公告)日：2023-06-15

申请号：US18105856

申请日：2023-02-05

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H10B80/00

CPC classification number: H10B80/00

Abstract: A semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; and a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells includes at least one second transistor, where the control circuits control access to the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least a portion of the array of memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.

公开(公告)号：US11621249B2

公开(公告)日：2023-04-04

申请号：US17396646

申请日：2021-08-06

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/473 ,  H01L23/66 ,  H01L25/00

Abstract: A 3D semiconductor device, the device including: a first level; and a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the second level is disposed above the first level and includes a plurality of arrays of memory cells, where the single crystal silicon includes an area, and where the area is greater than 1,000 mm2.

公开(公告)号：US11621240B2

公开(公告)日：2023-04-04

申请号：US17949988

申请日：2022-09-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells include at least one second transistor, where the control circuits control the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least one of the memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.