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    Ultra-Capacitor Based Energy Storage for Appliances
    31.
    发明申请
    Ultra-Capacitor Based Energy Storage for Appliances 审中-公开
    基于超电容器的电器储能

    公开(公告)号：US20130271092A1

    公开(公告)日：2013-10-17

    申请号：US13992717

    申请日：2011-12-30

    申请人： Shekhar Y. Borkar

    发明人： Shekhar Y. Borkar

    IPC分类号： H02J7/00

    CPC分类号： H02J50/05 ,  H01G11/14 ,  H02J7/007 ,  H02J7/025 ,  H02J7/34

    摘要： An ultra-capacitor may replace a rechargeable battery in consumer applications where the appliance usage is not prolonged. That is, if the usage is intermittent, the ultra-capacitor can quickly recharge between consecutive uses. Especially for those applications where an appliance spends most of the time on a charging cradle ultra-capacitor may efficiently replace batteries in appliances.

    摘要翻译： 超级电容器可以在消费者应用中替换可再充电电池，其中电器使用不会延长。 也就是说，如果使用是间歇性的，超级电容器可以在连续使用之间快速充电。 特别是对于家用电器大部分时间用于充电座的应用，超级电容器可以有效地更换电器中的电池。

    Integrated ultracapacitor as energy source
    33.
    发明授权
    Integrated ultracapacitor as energy source 有权
    集成超级电容器作为能源

    公开(公告)号：US07324328B2

    公开(公告)日：2008-01-29

    申请号：US11274187

    申请日：2005-11-16

    申请人： Siva G. Narendra ,  Shekhar Y. Borkar

    发明人： Siva G. Narendra ,  Shekhar Y. Borkar

    IPC分类号： H01G9/00

    CPC分类号： H01G9/155 ,  H01L23/5223 ,  H01L2924/0002 ,  Y02E60/13 ,  H01L2924/00

    摘要： An ultracapacitor formed on a semiconductor substrate includes a plurality conductive layers with intervening dielectric layers. These layers form a plurality of capacitors which may be connected in parallel to store a charge for powering an electronic circuit or for performing a variety of integrated circuit applications. A plurality of ultracapacitors of this type may be connected in series or may be designed in stacked configuration for attaining a specific charge distribution profile.

    摘要翻译： 形成在半导体衬底上的超级电容器包括具有中间介电层的多个导电层。 这些层形成多个电容器，其可以并联连接以存储用于为电子电路供电或用于执行各种集成电路应用的电荷。 这种类型的多个超级电容器可以串联连接或者可以被设计成堆叠配置以获得特定的电荷分布曲线。

    Integrated circuit stubs in a point-to-point system
    35.
    发明授权
    Integrated circuit stubs in a point-to-point system 有权
    集成电路存根在点对点系统中

    公开(公告)号：US06747474B2

    公开(公告)日：2004-06-08

    申请号：US09797480

    申请日：2001-02-28

    申请人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    发明人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

    IPC分类号： H03K1716

    CPC分类号： H04L5/14 ,  H03K19/01759 ,  H04L25/0278 ,  H04L25/24

    摘要： In some embodiments, the invention involves multiple integrated circuit stubs coupled in series. At least one of the integrated circuit stubs including first conductors to receive signals from a first adjacent one of the integrated circuit stubs, second conductors to provide signals to a second adjacent one of the integrated circuit stubs, and third conductors to provide signals to an integrated circuit chip. The integrated circuit stubs include first drivers and second drivers coupled to the first, second, and third conductors, wherein the first drivers receive the external signals from the first conductors and drive them onto the second conductors and the second drivers receive signals from the first conductors and drive them onto the third conductors.

    摘要翻译： 在一些实施例中，本发明涉及串联耦合的多个集成电路短截线。 所述集成电路短截线中的至少一个包括用于接收来自所述集成电路短截线中的第一相邻一个的信号的第一导体，用于向所述集成电路短截线中的第二相邻组件提供信号的第二导体以及向集成电路短截线提供信号的第三导体 电路芯片。 集成电路短截线包括耦合到第一，第二和第三导体的第一驱动器和第二驱动器，其中第一驱动器接收来自第一导体的外部信号并将它们驱动到第二导体上，并且第二驱动器从第一导体接收信号 并将它们驱动到第三导体上。

    Employing transistor body bias in controlling chip parameters
    38.
    发明授权
    Employing transistor body bias in controlling chip parameters 有权
    采用晶体管体偏置来控制芯片参数

    公开(公告)号：US06411156B1

    公开(公告)日：2002-06-25

    申请号：US09224575

    申请日：1998-12-30

    申请人： Shekhar Y. Borkar ,  Vivek K. De ,  Ali Keshavarzi ,  Siva G. Narendra

    发明人： Shekhar Y. Borkar ,  Vivek K. De ,  Ali Keshavarzi ,  Siva G. Narendra

    IPC分类号： H03K301

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  H01L27/0928 ,  H01L29/1087 ,  H03K19/00384 ,  H03K19/0948 ,  H03K2217/0018 ,  Y02D10/126 ,  Y02D10/172

    摘要： In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control a setting of a body bias signal to control body biases provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal being responsive to an input signal to the control circuitry. In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control settings of a body bias signal, a supply voltage signal, and a clock signal to control body biases, supply voltages, and clock frequencies provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal, supply voltage signal, and clock signal being responsive to an input signal to the control circuitry.

    摘要翻译： 在一些实施例中，本发明涉及包括集成电路的系统。 该系统包括晶体管的电路。 该系统还包括控制电路，用于控制体偏置信号的设置以控制设置在电路中的身体偏压，以至少部分地控制集成电路的参数，体偏置信号的设置响应于输入信号 控制电路。 在一些实施例中，本发明涉及包括集成电路的系统。 该系统包括晶体管的电路。 该系统还包括控制电路，用于控制体偏置信号，电源电压信号和时钟信号的设置，以控制电路中提供的体偏置，电源电压和时钟频率，以至少部分地控制集成电路的参数 ，所述体偏置信号，电源电压信号和时钟信号的设置响应于控制电路的输入信号。

    Soft error rate tolerant latch
    39.
    发明授权
    Soft error rate tolerant latch 有权
    软错误率容错锁存器

    公开(公告)号：US06380781B1

    公开(公告)日：2002-04-30

    申请号：US09430977

    申请日：1999-11-01

    申请人： Tanay Karnik ,  Krishnamurthy Soumyanath ,  Shekhar Y. Borkar

    发明人： Tanay Karnik ,  Krishnamurthy Soumyanath ,  Shekhar Y. Borkar

    IPC分类号： H03K312

    CPC分类号： G01R31/318525 ,  G01R31/31816

    摘要： A latch having increased soft error rate tolerance includes cross-coupled inverters having transistors with varying sizes. Diffusion regions of transistors coupled to storage nodes are kept small to reduce the effect of charge accumulation resulting from particles bombarding the bulk of an integrated circuit die. Transistors having gates coupled to the storage nodes are increased in size to increase the capacitance on the storage nodes. The reduced size of diffusion regions and increased size of gates on storage nodes combine to reduce the effects of accumulated charge. Diffusion region area is further reduced by reducing the size of pass gates that load normal data and scan data. A large capacitor is coupled to a feedback node within the cross-coupled inverters to further reduce the effect of accumulated charge.

    摘要翻译： 具有增加的软错误率容限的锁存器包括具有不同尺寸的晶体管的交叉耦合反相器。 耦合到存储节点的晶体管的扩散区域保持较小，以减少由颗粒轰击集成电路管芯的体积而产生的电荷累积的影响。 具有耦合到存储节点的栅极的晶体管的尺寸增加以增加存储节点上的电容。 扩散区尺寸减小，存储节点栅极尺寸增大，减少了累积电荷的影响。 通过减小加载正常数据和扫描数据的通孔的大小进一步减小扩散区域面积。 大电容器耦合到交叉耦合的反相器内的反馈节点，以进一步降低累积电荷的影响。

    Circuit including forward body bias from supply voltage and ground nodes
    40.
    发明授权
    Circuit including forward body bias from supply voltage and ground nodes 失效
    电路包括电源电压和接地节点的正向偏置

    公开(公告)号：US06300819B1

    公开(公告)日：2001-10-09

    申请号：US09078395

    申请日：1998-05-13

    申请人： Vivek K. De ,  Ali Keshavarzi ,  Siva G. Narendra ,  Shekhar Y. Borkar

    发明人： Vivek K. De ,  Ali Keshavarzi ,  Siva G. Narendra ,  Shekhar Y. Borkar

    IPC分类号： G05F110

    CPC分类号： H01L27/0928 ,  H01L29/1087 ,  H03K19/0948

    摘要： One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.

    摘要翻译： 本发明的一个实施例包括一个半导体电路，该半导体电路包括提供接地电压的接地电压节点和具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。 本发明的另一个实施例包括一个半导体电路，其包括提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型体的nFET晶体管，以使nFET晶体管的本体偏置转向。 本发明的另一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。 该电路还包括用于提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型主体的nFET晶体管，以使nFET晶体管的主体偏置转向。