公开(公告)号：US20090014720A1

公开(公告)日：2009-01-15

申请号：US12165365

申请日：2008-06-30

Applicant: Carlos MAZURE ,  Ian Cayrefourcq ,  Konstantin Bourdelle

Inventor： Carlos MAZURE ,  Ian Cayrefourcq ,  Konstantin Bourdelle

IPC: H01L21/30 ,  H01L29/04

CPC classification number: H01L21/187 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/76254 ,  H01L29/045

Abstract: The present invention relates to a method of treating a structure produced from semiconductor materials, wherein the structure includes a first and second substrates defining a common interface that has defects. The method includes forming a layer, called the disorganized layer, which includes the interface, in which at least a part of the crystal lattice is disorganized; and reorganizing the crystal lattice of the disorganized layer in order to force the defects back deeper into the first substrate.

Abstract translation: 本发明涉及一种处理由半导体材料制成的结构的方法，其中该结构包括限定具有缺陷的公共接口的第一和第二基板。 所述方法包括形成称为所述无组织层的层，所述层包括所述界面，其中所述晶格的至少一部分被混杂; 并重新组织无组织层的晶格，以迫使缺陷更深地进入第一衬底。

公开(公告)号：US20080303061A1

公开(公告)日：2008-12-11

申请号：US11910104

申请日：2006-03-29

Applicant: Konstantin Bourdelle ,  Carlos Mazure

Inventor： Konstantin Bourdelle ,  Carlos Mazure

IPC: H01L21/265 ,  H01L21/762 ,  H01L29/161

CPC classification number: H01L21/26506 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02694

Abstract: A process for the manufacture of a substrate having a top layer of a first material and an underlying layer of a second material whose lattice parameter is different from that of the first material. The process includes the steps of conducting an amorphization of the top layer to create an amorphous region in the top layer lying between an exposed surface and an amorphization interface, with that portion of the top layer below the interface being shielded from the amorphization and remaining as a crystalline structure; recrystallizing the amorphous region while also creating a network of defects at the interface, wherein the network forms a boundary for dislocations from the crystalline structure of the top layer, and containing the dislocations in the portion of the top layer that is located below the interface. Also, the substrates obtained by the method.

Abstract translation: 一种用于制造具有第一材料的顶层和其晶格参数不同于第一材料的第二材料的下层的衬底的方法。 该方法包括以下步骤：顶层的非晶化，以在位于暴露表面和非晶化界面之间的顶层中形成非晶区域，该界面下面的顶层部分被遮蔽以及非晶化，并保留为 晶体结构; 重结晶非晶区域同时也在界面处产生缺陷网络，其中网络形成与顶层的晶体结构的位错的边界，并且包含位于界面下方的顶层部分中的位错。 另外，通过该方法得到的基板。

公开(公告)号：US07407548B2

公开(公告)日：2008-08-05

申请号：US10916254

申请日：2004-08-11

Applicant: Konstantin Bourdelle ,  Ian Cayrefourcq ,  Mark Kennard

Inventor： Konstantin Bourdelle ,  Ian Cayrefourcq ,  Mark Kennard

IPC: C30B25/04

CPC classification number: H01L21/0262 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532

Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.

Abstract translation: 本发明涉及一种制造晶片的方法，该方法包括第一材料的单晶体体衬底和具有与第一材料的晶格不同的晶格的第二材料的至少一个外延层。 本发明提供了一种制造晶片的方法，其中可以以低成本以高效率和高质量在衬底上生长与衬底晶格失配的层。 包括粗糙化步骤以粗化本体衬底的表面，并且包括生长步骤，用于在粗糙表面上生长第二材料，数量较少的穿透位错和与外延生长的第二材料相比增强的应变松弛 抛光表面。

公开(公告)号：US20080102601A1

公开(公告)日：2008-05-01

申请号：US11877456

申请日：2007-10-23

Applicant: Konstantin Bourdelle ,  Carlos Mazure

Inventor： Konstantin Bourdelle ,  Carlos Mazure

IPC: H01L21/30

CPC classification number: H01L21/02667 ,  H01L21/2022 ,  H01L21/76254

Abstract: This invention relates to a method for producing a substrate by transferring a layer of a material from a donor substrate to a support substrate, and then by removing a part of the layer of material to form the thin layer. The step of removing a part of the layer of material to form the thin layer comprises forming an amorphous layer in a part of the thin layer, and then recrystallizing the amorphous layer.

Abstract translation: 本发明涉及一种通过将材料层从供体衬底转移到支撑衬底，然后通过移除材料层的一部分以形成薄层来制造衬底的方法。 除去材料层的一部分以形成薄层的步骤包括在薄层的一部分中形成非晶层，然后使非晶层重结晶。

公开(公告)号：US20070281445A1

公开(公告)日：2007-12-06

申请号：US10577175

申请日：2004-10-28

Applicant: Nguyet-Phuong Nguyen ,  Ian Cayrefourcq ,  Christelle Lagahe-Blanchard ,  Konstantin Bourdelle ,  Aurelie Tauzin ,  Franck Fournel

Inventor： Nguyet-Phuong Nguyen ,  Ian Cayrefourcq ,  Christelle Lagahe-Blanchard ,  Konstantin Bourdelle ,  Aurelie Tauzin ,  Franck Fournel

IPC: H01L21/304

CPC classification number: H01L21/76254

Abstract: A method for self-supported transfer of a fine layer, in which at least one species of ions is implanted in a source-substrate at a specified depth in relation to the surface of the source-substrate. A stiffener is applied in intimate contact with the source-substrate and the source-substrate undergoes a heat treatment at a specified temperature during a specified period of time in order to create an embrittled buried area substantially at the specified depth without causing a thin layer, defined between the surface and the embrittled buried layer in relation to the remainder of the source-substrate, to become thermally detached. A controlled localized energy pulse is applied to the source-substrate in order to cause the self-supported detachment of the thin layer.

Abstract translation: 一种用于自支撑转移细层的方法，其中将至少一种离子注入相对于源 - 衬底表面的指定深度的源极 - 衬底中。 施加加强件以与源 - 基板紧密接触，并且源 - 基板在特定时间段内在特定温度下进行热处理，以便在基本上在指定深度处产生脆弱的掩埋区域而不产生薄层， 相对于源极 - 基板的其余部分，在表面和脆化的掩埋层之间限定为热分离。 将受控的局部能量脉冲施加到源 - 衬底，以引起薄层的自支撑分离。

公开(公告)号：US20070134887A1

公开(公告)日：2007-06-14

申请号：US11677696

申请日：2007-02-22

Applicant: Konstantin Bourdelle ,  Nicolas Daval ,  Ian Cayrefourcq ,  Steven Van Aerde ,  Marinus De Blank ,  Cornelius Van Der Jeugd

Inventor： Konstantin Bourdelle ,  Nicolas Daval ,  Ian Cayrefourcq ,  Steven Van Aerde ,  Marinus De Blank ,  Cornelius Van Der Jeugd

IPC: H01L21/473

CPC classification number: H01L21/31612 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02271

Abstract: The invention relates to a of manufacturing a silicon dioxide layer of low roughness, that includes depositing a layer of silicon dioxide over a substrate by a low pressure chemical vapour deposition (LPCVD) process, the deposition process employing simultaneously a flow of tetraethylorthosilicate (TEOS) as the source material for the film deposition and a flow of a diluant gas that it not reactive with TEOS, so that the diluant gas/TEOS flow ratio is between 0.5 and 100; and annealing the silicon dioxide layer at a temperature between 600° C. and 1200° C., for a duration between 10 minutes and 6 hours.

Abstract translation: 本发明涉及一种制造低粗糙度的二氧化硅层的方法，其包括通过低压化学气相沉积（LPCVD）工艺在衬底上沉积二氧化硅层，该沉积工艺同时采用原硅酸四乙酯（TEOS ）作为膜沉积的源材料和与TEOS不反应的稀释气体流，使得稀释气体/ TEOS流量比在0.5和100之间; 并在600℃和1200℃之间的温度下将二氧化硅层退火10分钟至6小时。

公开(公告)号：US20070000435A1

公开(公告)日：2007-01-04

申请号：US11518366

申请日：2006-09-08

Applicant: Konstantin Bourdelle ,  Ian Cayrefourcq ,  Mark Kennard

Inventor： Konstantin Bourdelle ,  Ian Cayrefourcq ,  Mark Kennard

IPC: C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC classification number: H01L21/0262 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532

Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.

Abstract translation: 本发明涉及一种制造晶片的方法，该方法包括第一材料的单晶体体衬底和具有与第一材料的晶格不同的晶格的第二材料的至少一个外延层。 本发明提供了一种制造晶片的方法，其中可以以低成本以高效率和高质量在衬底上生长与衬底晶格失配的层。 包括粗糙化步骤以粗化本体衬底的表面，并且包括生长步骤，用于在粗糙表面上生长第二材料，数量较少的穿透位错和与外延生长的第二材料相比增强的应变松弛 抛光表面。

公开(公告)号：US20060110899A1

公开(公告)日：2006-05-25

申请号：US11029808

申请日：2005-01-04

Applicant: Konstantin Bourdelle ,  Fabrice Letertre ,  Bruce Faure ,  Christophe Morales ,  Chrystel Deguet

Inventor： Konstantin Bourdelle ,  Fabrice Letertre ,  Bruce Faure ,  Christophe Morales ,  Chrystel Deguet

IPC: H01L21/20

CPC classification number: H01L21/76254

Abstract: Improved fabrication processes for manufacturing GeOI type wafers are disclosed. In an implementation, a method for fabricating a germanium on insulator wafer includes providing a source substrate having a surface, at least a layer of germanium and a weakened area. The weakened area is located at a predetermined depth in the germanium layer of the source substrate and is generally parallel to the source substrate surface. The technique also includes providing a germanium oxynitride layer in or on the source substrate, bonding the source substrate surface to a handle substrate to form a source-handle structure, and detaching the source substrate from the source-handle structure at the weakened area of the source substrate to create the germanium on insulator wafer having, as a surface, a useful layer of germanium.

Abstract translation: 公开了用于制造GeOI型晶片的改进的制造工艺。 在一个实施方案中，用于制造绝缘体上硅晶片的方法包括提供具有表面，至少一层锗和弱化区域的源极衬底。 弱化区域位于源极衬底的锗层中的预定深度处，并且大致平行于源极衬底表面。 该技术还包括在源极衬底中或其上提供氮氧化锗层，将源极衬底表面接合到处理衬底上以形成源极 - 手柄结构，以及在源极 - 手柄结构的弱化区域处将源极衬底与源极 - 源衬底以形成绝缘体上的晶圆，其具有作为表面的锗的有用层。

公开(公告)号：US20050245049A1

公开(公告)日：2005-11-03

申请号：US11179713

申请日：2005-07-11

Applicant: Takeshi Akatsu ,  Nicolas Daval ,  Nguyet-Phuong Nguyen ,  Olivier Rayssac ,  Konstantin Bourdelle

Inventor： Takeshi Akatsu ,  Nicolas Daval ,  Nguyet-Phuong Nguyen ,  Olivier Rayssac ,  Konstantin Bourdelle

IPC: H01L21/762 ,  H01L21/30 ,  H01L21/46

CPC classification number: H01L21/76254

Abstract: Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface; coimplanting two different atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer; bonding the free surface of the second layer to a host wafer; and supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer. Advantageously, the donor wafer includes a SiGe layer, and the co-implantation of atomic species is conducted according to implantation parameters adapted to enable a first species to form the zone of weakness in the SiGe layer, and to enable a second species to provide a concentration peak located beneath the zone of weakness in the donor wafer to thus minimize surface roughness resulting from detachment at the zone of weakness.

Abstract translation: 描述形成半导体结构的方法。 在一个实施例中，该技术包括提供在第一层上具有第一半导体层和第二半导体层并具有自由表面的施主晶片; 通过第二层的自由表面共同植入两种不同的原子物质，以形成第一层中的弱区; 将第二层的自由表面粘合到主晶片; 并且在弱化区域提供能量以分散包含主晶片，第二层和第一层的一部分的半导体结构。 有利地，施主晶片包括SiGe层，并且根据适于使第一种类形成SiGe层中的弱点区域的植入参数来进行原子物质的共同注入，并且使得第二物质能够提供 浓度峰位于供体晶片中的弱点之下，从而使得在弱化区分离导致的表面粗糙度最小化。