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    Non-volatile semiconductor device
    31.
    发明授权
    Non-volatile semiconductor device 失效
    非易失性半导体器件

    公开(公告)号：US07889552B2

    公开(公告)日：2011-02-15

    申请号：US12068409

    申请日：2008-02-06

    申请人： Jae-chul Park ,  Jae-woong Hyun ,  Young-soo Park ,  Sun-il Kim

    发明人： Jae-chul Park ,  Jae-woong Hyun ,  Young-soo Park ,  Sun-il Kim

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A nonvolatile semiconductor device according to example embodiments may include a plurality of memory cells on a semiconductor substrate and at least one selection transistor on the semiconductor substrate, wherein the at least one selection transistor may be disposed at a different level from the plurality of memory cells. The at least one selection transistor may be connected to a data line and/or a power source line via a first contact and/or a third contact, respectively. The at least one selection transistor may be connected to the plurality of memory cells via a second contact and/or a fourth contact. The active layer of the at least one selection transistor may contain an oxide. Accordingly, the nonvolatile semiconductor device according to example embodiments may include a selection transistor having a reduced size.

    摘要翻译： 根据示例实施例的非易失性半导体器件可以包括半导体衬底上的多个存储单元和半导体衬底上的至少一个选择晶体管，其中所述至少一个选择晶体管可以设置在与所述多个存储单元不同的电平 。 所述至少一个选择晶体管可以分别经由第一触点和/或第三触点连接到数据线和/或电源线。 所述至少一个选择晶体管可以经由第二触点和/或第四触点连接到所述多个存储单元。 所述至少一个选择晶体管的有源层可以含有氧化物。 因此，根据示例性实施例的非易失性半导体器件可以包括具有减小的尺寸的选择晶体管。

    Nonvolatile memory devices and data reading methods
    32.
    发明授权
    Nonvolatile memory devices and data reading methods 有权
    非易失性存储器件和数据读取方法

    公开(公告)号：US07839694B2

    公开(公告)日：2010-11-23

    申请号：US12076706

    申请日：2008-03-21

    申请人： In-sung Joe ,  Young-gu Jin ,  Jae-woong Hyun ,  Yoon-dong Park

    发明人： In-sung Joe ,  Young-gu Jin ,  Jae-woong Hyun ,  Yoon-dong Park

    IPC分类号： G11C16/06

    CPC分类号： G11C16/3418

    摘要： Methods of reading memory cell data and nonvolatile memory devices, which apply a low voltage to memory cells adjacent to a memory cell from which data may be read are provided. Methods of reading memory cell data of nonvolatile memory device include applying a first voltage to a control gate of a read memory cell from among the plurality of memory cells, applying a third voltage to control gates of memory cell adjacent to the read memory cell, and applying a second voltage to control gates of memory cells other than the read memory cell and the adjacent memory cells.

    摘要翻译： 提供将存储单元数据和非易失性存储器件读取的方法，该存储单元数据和非易失性存储器件将低电压施加到与可读取数据的存储器单元相邻的存储器单元。 读取非易失性存储器件的存储单元数据的方法包括从多个存储器单元向读存储器单元的控制栅极施加第一电压，将第三电压施加到与读存储单元相邻的存储单元的控制栅极，以及 将第二电压施加到除了读存储器单元和相邻存储单元之外的存储单元的控制栅极。

    Non-volatile semiconductor device
    34.
    发明申请
    Non-volatile semiconductor device 失效
    非易失性半导体器件

    公开(公告)号：US20090003062A1

    公开(公告)日：2009-01-01

    申请号：US12068409

    申请日：2008-02-06

    申请人： Jae-chul Park ,  Jae-woong Hyun ,  Young-soo Park ,  Sun-il Kim

    发明人： Jae-chul Park ,  Jae-woong Hyun ,  Young-soo Park ,  Sun-il Kim

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A nonvolatile semiconductor device according to example embodiments may include a plurality of memory cells on a semiconductor substrate and at least one selection transistor on the semiconductor substrate, wherein the at least one selection transistor may be disposed at a different level from the plurality of memory cells. The at least one selection transistor may be connected to a data line and/or a power source line via a first contact and/or a third contact, respectively. The at least one selection transistor may be connected to the plurality of memory cells via a second contact and/or a fourth contact. The active layer of the at least one selection transistor may contain an oxide. Accordingly, the nonvolatile semiconductor device according to example embodiments may include a selection transistor having a reduced size.

    摘要翻译： 根据示例性实施例的非易失性半导体器件可以包括半导体衬底上的多个存储单元和半导体衬底上的至少一个选择晶体管，其中所述至少一个选择晶体管可以设置在与所述多个存储单元不同的电平 。 所述至少一个选择晶体管可以分别经由第一触点和/或第三触点连接到数据线和/或电源线。 所述至少一个选择晶体管可以经由第二触点和/或第四触点连接到所述多个存储单元。 所述至少一个选择晶体管的有源层可以含有氧化物。 因此，根据示例性实施例的非易失性半导体器件可以包括具有减小的尺寸的选择晶体管。

    Methods of operating a non-volatile memory device
    36.
    发明申请
    Methods of operating a non-volatile memory device 有权
    操作非易失性存储器件的方法

    公开(公告)号：US20080013373A1

    公开(公告)日：2008-01-17

    申请号：US11826059

    申请日：2007-07-12

    申请人： Yoon-dong Park ,  Kyoung-lee Cho ,  Jae-woong Hyun ,  Sung-jae Byun

    发明人： Yoon-dong Park ,  Kyoung-lee Cho ,  Jae-woong Hyun ,  Sung-jae Byun

    IPC分类号： G11C11/56

    CPC分类号： G11C11/5685 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/31

    摘要： Example embodiments provide a method of operating a nonvolatile memory device in a multi-bit mode, which may operate at a low operating current and may be more integrated. In example embodiments, a first buried electrode may be used as a first bit line and a second buried electrode may be used as a second bit line, and a gate electrode may be used as a word line. Example methods may include programming 2-bit data to first and second resistance layers and reading the 2-bit data programmed in the first and second resistance layers. Example methods may include programming and reading more than 2-bit data using more than 2 buried electrodes.

    摘要翻译： 示例性实施例提供了以多位模式操作非易失性存储器件的方法，其可以在低工作电流下操作并且可以更加集成。 在示例性实施例中，第一掩埋电极可以用作第一位线，并且第二掩埋电极可以用作第二位线，并且栅电极可以用作字线。 示例性方法可以包括将2位数据编程到第一和第二电阻层并读取在第一和第二电阻层中编程的2位数据。 示例性方法可以包括使用多于2个掩埋电极编程和读取多于2位的数据。

    Non-volatile memory device including block state confirmation cell and method of operating the same
    37.
    发明授权
    Non-volatile memory device including block state confirmation cell and method of operating the same 有权
    包括块状态确认单元的非易失性存储器件及其操作方法

    公开(公告)号：US08050087B2

    公开(公告)日：2011-11-01

    申请号：US12071349

    申请日：2008-02-20

    申请人： Ju-hee Park ,  Jae-woong Hyun ,  Kyoung-lae Cho ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kee-won Kwon

    发明人： Ju-hee Park ,  Jae-woong Hyun ,  Kyoung-lae Cho ,  Yoon-dong Park ,  Seung-hoon Lee ,  Kee-won Kwon

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C11/5642 ,  G11C2211/5641 ,  G11C2211/5646

    摘要： Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell.

    摘要翻译： 提供了具有块状态确认单元的半导体器件，其可以存储指示写入多个存储器单元的数据位数的信息，基于写入的数据位的数量读取存储器数据的方法和/或存储器 存储指示写入数据位数的信息的编程方法。 半导体器件可以包括一个或多个存储器块和控制器。 每个存储器块可以包括存储数据的多个存储单元，以及存储指示写入存储单元的数据位数的信息的块状态确认单元。 控制器可以基于在块状态确认单元中的信息中指示的数据位数来从存储器块读取数据位。

    Method of programming multi-level semiconductor memory device and multi-level semiconductor memory device
    39.
    发明授权
    Method of programming multi-level semiconductor memory device and multi-level semiconductor memory device 有权
    编程多电平半导体存储器件和多电平半导体存储器件的方法

    公开(公告)号：US07577042B2

    公开(公告)日：2009-08-18

    申请号：US11978578

    申请日：2007-10-30

    申请人： Jae-woong Hyun ,  Kyoung-lae Cho ,  Kyu-charn Park ,  Yoon-dong Park ,  Choong-ho Lee ,  Sung-jae Byun

    发明人： Jae-woong Hyun ,  Kyoung-lae Cho ,  Kyu-charn Park ,  Yoon-dong Park ,  Choong-ho Lee ,  Sung-jae Byun

    IPC分类号： G11C7/00

    CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C2211/5642

    摘要： Provided in one example embodiment, a method of programming n bits of data to a semiconductor memory device may include outputting a first bit of data written in a memory cell from a first latch, storing the first bit of the data to a third latch, storing a second bit of the data to the first latch, outputting the second bit of the data from the first latch, storing the second bit of the data to the second latch, and writing the second bit of the data stored in the second latch to the memory cell with reference to a data storage state of the first bit of the data stored in the third latch.

    摘要翻译： 在一个示例性实施例中提供了一种将半位数据数据编程到半导体存储器件的方法可以包括从第一锁存器输出写入存储器单元中的第一位数据，将第一位数据存储到第三锁存器，存储 将数据的第二位输出到第一锁存器，从第一锁存器输出数据的第二位，将数据的第二位存储到第二锁存器，以及将存储在第二锁存器中的数据的第二位写入到 参考存储在第三锁存器中的数据的第一位的数据存储状态的存储器单元。

    Unit cell of a non-volatile memory device, a non-volatile memory device and method thereof
    40.
    发明授权
    Unit cell of a non-volatile memory device, a non-volatile memory device and method thereof 有权
    非易失性存储器件的单元，非易失性存储器件及其方法

    公开(公告)号：US07551491B2

    公开(公告)日：2009-06-23

    申请号：US11715404

    申请日：2007-03-08

    申请人： Won-joo Kim ,  Suk-pil Kim ,  Jae-woong Hyun ,  Yoon-dong Park ,  June-mo Koo

    发明人： Won-joo Kim ,  Suk-pil Kim ,  Jae-woong Hyun ,  Yoon-dong Park ,  June-mo Koo

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0433 ,  G11C16/0491 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

    摘要： Unit cells of a non-volatile memory device and a method thereof are provided. In an example, the unit cell may include a first memory transistor and a second memory transistor connected to each other in series and further connected in common to a word line, the first and second memory transistors including first and second storage nodes, respectively, the first and second storage nodes configured to execute concurrent memory operations. In another example, the unit cell may include a semiconductor substrate in which first and second bit line regions are defined, first and second storage node layers respectively formed on the semiconductor substrate between the first and second bit line regions, a first pass gate electrode formed on the semiconductor substrate between the first bit line region and the first storage node layer, a second pass gate electrode formed on the semiconductor substrate between the second bit line region and the second storage node layer, a third pass gate electrode formed on the semiconductor substrate between the first and second storage node layers, a third bit line region formed in a portion of the semiconductor substrate under the third pass gate electrode and a control gate electrode extending across the first and second storage node layers. The example unit cells may be implemented within a non-volatile memory device (e.g., a flash memory device), such that the non-volatile memory device may include a plurality of example unit cells.

    摘要翻译： 提供非易失性存储器件的单元电池及其方法。 在一个示例中，单元可以包括串联连接并进一步连接到字线的第一存储晶体管和第二存储晶体管，第一和第二存储晶体管分别包括第一和第二存储节点， 配置为执行并发存储器操作的第一和第二存储节点。 在另一示例中，单元可以包括其中限定了第一和第二位线区域的半导体衬底，分别形成在第一和第二位线区域之间的半导体衬底上的第一和第二存储节点层，形成的第一遍栅极电极 在第一位线区域和第一存储节点层之间的半导体衬底上，形成在第二位线区域和第二存储节点层之间的半导体衬底上的第二遍栅极电极，形成在半导体衬底上的第三栅极电极 在所述第一和第二存储节点层之间形成第三位线区域，所述第三位线区域形成在所述第三栅极电极下方的所述半导体衬底的一部分中，以及跨越所述第一和第二存储节点层延伸的控制栅电极。 示例性单元单元可以在非易失性存储器件（例如，闪存器件）内实现，使得非易失性存储器件可以包括多个示例单位单元。