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31.发明授权公开(公告)号：US10339094B2
公开(公告)日：2019-07-02
申请号：US14716216
申请日：2015-05-19
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola , Vitaly Kalashnikov , Sitij Agrawal
Abstract: A computer processor is disclosed. The computer processor comprises one or more processor resources. The computer processor further comprises a plurality of hardware thread units coupled to the one or more processor resources. The computer processor may be configured to permit simultaneous access to the one or more processor resources by only a subset of hardware thread units of the plurality of hardware thread units. The number of hardware threads in the subset may be less than the total number of hardware threads of the plurality of hardware thread units.
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32.发明授权公开(公告)号：US09792116B2
公开(公告)日：2017-10-17
申请号：US15087204
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC: G06F12/10 , G06F9/30 , G06F3/06 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F12/0862 , G06F9/32 , G06F9/355
CPC classification number: G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F2212/452 , G06F2212/60 , G06F2212/602
Abstract: A computer processor that implements pre-translation of virtual addresses with target registers is disclosed. The computer processor may include a register file comprising one or more registers. The computer processor may include processing logic. The processing logic may receive a value to store in a register of one or more registers. The processing logic may store the value in the register. The processing logic may designate the received value as a virtual instruction address, the virtual instruction address having a corresponding virtual base page number. The processing logic may translate the virtual base page number to a corresponding real base page number and zero or more real page numbers corresponding to zero or more virtual page numbers adjacent to the virtual base page number. The processing logic may further store in the register of the one or more registers the real base page number and the zero or more real page numbers.
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33.发明申请COMPUTER PROCESSOR THAT IMPLEMENTS PRE-TRANSLATION OF VIRTUAL ADDRESSES WITH TARGET REGISTERS 有权计算机处理器，实现对目标寄存器的虚拟地址的预翻译公开(公告)号：US20160314075A1
公开(公告)日：2016-10-27
申请号：US15087204
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
CPC classification number: G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F2212/452 , G06F2212/60 , G06F2212/602
Abstract: A computer processor that implements pre-translation of virtual addresses with target registers is disclosed. The computer processor may include a register file comprising one or more registers. The computer processor may include processing logic. The processing logic may receive a value to store in a register of one or more registers. The processing logic may store the value in the register. The processing logic may designate the received value as a virtual instruction address, the virtual instruction address having a corresponding virtual base page number. The processing logic may translate the virtual base page number to a corresponding real base page number and zero or more real page numbers corresponding to zero or more virtual page numbers adjacent to the virtual base page number. The processing logic may further store in the register of the one or more registers the real base page number and the zero or more real page numbers.
Abstract translation: 公开了一种实现虚拟地址与目标寄存器的预翻译的计算机处理器。 计算机处理器可以包括包括一个或多个寄存器的寄存器文件。 计算机处理器可以包括处理逻辑。 处理逻辑可以接收一个值以存储在一个或多个寄存器的寄存器中。 处理逻辑可以将该值存储在寄存器中。 处理逻辑可以将接收的值指定为虚拟指令地址，虚拟指令地址具有对应的虚拟基本页码。 处理逻辑可以将虚拟基页编号转换为对应的真实基页编号和对应于与虚拟基页编号相邻的零个或多个虚拟页码的零个或多个实际页号。 处理逻辑还可以在一个或多个寄存器的寄存器中存储真实的基页号码和零个或多个实际页码。
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34.发明申请VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS WITH OUT-OF-ORDER EXECUTION 审中-公开矢量处理器被配置为使用可变长度矢量进行操作，不合格的执行公开(公告)号：US20160224513A1
公开(公告)日：2016-08-04
申请号：US14718740
申请日：2015-05-21
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Murugappan Senthilvelan , Pablo Balzola
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F9/461 , G06F9/462 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor is disclosed. The computer processor comprise a vector unit comprising a vector register file comprising at least one vector register to hold a varying number of elements. The computer processor further comprises out-of-order issue logic that holds a pool of vector instructions, selects a vector instruction from the pool, and sends the vector instruction for execution. The vector instruction operates on the varying number of elements of the at least one vector register.
Abstract translation: 公开了一种计算机处理器。 计算机处理器包括矢量单元，其包括矢量寄存器文件，该矢量寄存器文件包括至少一个矢量寄存器以保存不同数量的元件。 计算机处理器还包括保存向量指令池的无序发行逻辑，从池中选择向量指令，并发送用于执行的向量指令。 向量指令对至少一个向量寄存器的元素的变化数量进行操作。
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35.发明申请MONOLITHIC VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS 审中-公开配置为可变长度矢量图的单片矢量处理器公开(公告)号：US20160224512A1
公开(公告)日：2016-08-04
申请号：US14709730
申请日：2015-05-12
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola , Vitaly Kalashnikov , Sitij Agrawal
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F9/461 , G06F9/462 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor comprising a vector unit is disclosed. The vector unit may comprise a vector register file comprising at least one register to hold a varying number of elements. The vector unit may further comprise a vector length register file comprising at least one register to specify the number of operations of a vector instruction to be performed on the varying number of elements in the at least one register of the vector register file. The computer processor may be implemented as a monolithic integrated circuit.
Abstract translation: 公开了一种包括向量单元的计算机处理器。 向量单元可以包括向量寄存器文件，其包括至少一个寄存器以保存不同数量的元素。 向量单元还可以包括向量长度寄存器文件，其包括至少一个寄存器，用于指定要对向量寄存器堆的至少一个寄存器中的变化数量的元素执行的向量指令的操作次数。 计算机处理器可以被实现为单片集成电路。
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Patent Agency Ranking
36.发明申请VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING IMPLICITLY TYPED INSTRUCTIONS 有权矢量处理器配置为使用明确的类型说明可变长度矢量公开(公告)号：US20160224511A1
公开(公告)日：2016-08-04
申请号：US14728522
申请日：2015-06-02
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Vitaly Kalashnikov
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor may further comprise processing logic configured to implicitly type each of the varying number of elements in the vector register file. The computer processor may be implemented as a monolithic integrated circuit.
Abstract translation: 公开了一种计算机处理器。 计算机处理器可以包括矢量单元，其包括矢量寄存器文件，其包括一个或多个寄存器以保存不同数量的元件。 计算机处理器还可以包括处理逻辑，其被配置为隐含地对向量寄存器文件中的各种变化数量的元素进行键入。 计算机处理器可以被实现为单片集成电路。
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37.发明申请VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS WITH ASYMMETRIC MULTI-THREADING 审中-公开矢量处理器配置为使用不对称多路径的可变长度矢量公开(公告)号：US20160224509A1
公开(公告)日：2016-08-04
申请号：US14716216
申请日：2015-05-19
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola , Vitaly Kalashnikov , Sitij Agrawal
IPC: G06F15/80
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F9/461 , G06F9/462 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor is disclosed. The computer processor comprises one or more processor resources. The computer processor further comprises a plurality of hardware thread units coupled to the one or more processor resources. The computer processor may be configured to permit simultaneous access to the one or more processor resources by only a subset of hardware thread units of the plurality of hardware thread units. The number of hardware threads in the subset may be less than the total number of hardware threads of the plurality of hardware thread units.
Abstract translation: 公开了一种计算机处理器。 计算机处理器包括一个或多个处理器资源。 计算机处理器还包括耦合到一个或多个处理器资源的多个硬件线程单元。 计算机处理器可以被配置为仅通过多个硬件线程单元中的硬件线程单元的子集来同时访问一个或多个处理器资源。 子集中的硬件线程的数量可以小于多个硬件线程单元中的硬件线程的总数。
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38.发明申请VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING INSTRUCTIONS TO COMBINE AND SPLIT VECTORS 有权使用指令组合和分割矢量配置可变长度矢量的矢量处理器公开(公告)号：US20160224346A1
公开(公告)日：2016-08-04
申请号：US14727076
申请日：2015-06-01
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more instructions that separate a vector or combine two vectors. The computer processor may be implemented as a monolithic integrated circuit.
Abstract translation: 公开了一种计算机处理器。 计算机处理器可以包括向量单元，其包括向量寄存器文件，其包括至少一个寄存器以保存不同数量的元件。 计算机处理器还可以包括处理逻辑，其被配置为使用分离向量或组合两个向量的一个或多个指令对向量寄存器文件中的变化数量的元素进行操作。 计算机处理器可以被实现为单片集成电路。
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39.发明申请VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING INSTRUCTIONS THAT CHANGE ELEMENT WIDTHS 审中-公开矢量处理器配置为可变长度矢量图，使用说明更改元素宽度公开(公告)号：US20160224345A1
公开(公告)日：2016-08-04
申请号：US14727051
申请日：2015-06-01
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Arthur Joseph Hoane , Paul Hurtley
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F9/461 , G06F9/462 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor is disclosed. The computer processor may comprises a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more instructions that produce results with elements of widths different than that of the input elements. The computer processor may be implemented as a monolithic integrated circuit.
Abstract translation: 公开了一种计算机处理器。 计算机处理器可以包括矢量单元，其包括矢量寄存器文件，该矢量寄存器文件包括至少一个寄存器以保存不同数量的元件。 计算机处理器还可以包括处理逻辑，其被配置为使用产生具有与输入元素的宽度不同的元素的结果的一个或多个指令对向量寄存器文件中的变化数量的元素进行操作。 计算机处理器可以被实现为单片集成电路。
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40.发明申请VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING DIGITAL SIGNAL PROCESSING INSTRUCTIONS 审中-公开使用数字信号处理指令配置在可变长度矢量上运行的矢量处理器公开(公告)号：US20160224344A1
公开(公告)日：2016-08-04
申请号：US14716285
申请日：2015-05-19
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola , Vitaly Kalashnikov , Sitij Agrawal
CPC classification number: G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F9/461 , G06F9/462 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
Abstract: A computer processor is disclosed. The computer processor comprises a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor further comprises processing logic configured to operate on the varying number of elements in the vector register file using one or more digital signal processing instructions. The computer processor may be implemented as a monolithic integrated circuit.
Abstract translation: 公开了一种计算机处理器。 计算机处理器包括矢量单元，其包括矢量寄存器文件，该矢量寄存器文件包括一个或多个寄存器以保存不同数量的元件。 计算机处理器还包括处理逻辑，其被配置为使用一个或多个数字信号处理指令对矢量寄存器文件中的变化数量的元件进行操作。 计算机处理器可以被实现为单片集成电路。
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