公开(公告)号：US20070114616A1

公开(公告)日：2007-05-24

申请号：US11287151

申请日：2005-11-23

申请人： Dirk Manger ,  Till Schloesser

发明人： Dirk Manger ,  Till Schloesser

IPC分类号： H01L29/76

CPC分类号： H01L29/4983 ,  H01L21/2815 ,  H01L27/10873 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： A field effect transistor, which is arranged in a semiconductor device, comprises a first and a second doped source/drain region, both regions being arranged within a semiconductor substrate on either side of a gate electrode, and a channel region formed within the substrate between both doped source/drain regions beneath said gate electrode. A gate oxide layer is formed upon the semiconductor substrate. The gate electrode contacts a surface of the gate oxide layer and further comprises at least a first and a second conductive layer, wherein the first and second conductive layers are made of materials having different work functions with respect to each other. The first conductive layer contacts the gate oxide layer within a first portion of the surface, and the second conductive layer contacts the gate oxide layer within a second portion of the surface. The first conductive layer is further conductively connected to the second conductive layer.

摘要翻译： 布置在半导体器件中的场效应晶体管包括第一和第二掺杂源极/漏极区域，两个区域布置在栅电极的任一侧上的半导体衬底内，以及形成在衬底内的沟道区域 在所述栅电极下方的掺杂源/漏区两者。 在半导体衬底上形成栅氧化层。 栅极电极接触栅极氧化物层的表面，并且还包括至少第一和第二导电层，其中第一和第二导电层由相对于彼此具有不同功函数的材料制成。 第一导电层在表面的第一部分内接触栅极氧化物层，并且第二导电层在表面的第二部分内接触栅极氧化物层。 第一导电层进一步导电连接到第二导电层。

公开(公告)号：US20070075361A1

公开(公告)日：2007-04-05

申请号：US11529446

申请日：2006-09-28

申请人： Richard Luyken ,  Hans-Peter Moll ,  Martin Popp ,  Till Schloesser ,  Marc Strasser ,  Rolf Weis

发明人： Richard Luyken ,  Hans-Peter Moll ,  Martin Popp ,  Till Schloesser ,  Marc Strasser ,  Rolf Weis

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L21/26586 ,  H01L29/66537 ,  H01L29/66621 ,  H01L29/7834

摘要： In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

摘要翻译： 在制造沟槽晶体管的方法中，提供第一导电类型的衬底，并且形成衬底中的沟槽和沟槽中的栅极电介质。 形成沟槽中作为栅极电介质和第一源极和漏极区域上的栅电极的第一导电填充物。 蚀刻后的第一导电填充物是通过将第一导电填料向下蚀刻回到低于第一源的深度并形成漏极区和第二源极和漏极区而产生的。 第二源极和漏极区域与第一源极和漏极区域相邻并且延伸至至少与蚀刻后的第一导电填充物一样深的深度。 在所述沟槽中形成有在所述蚀刻后的第一导电填充物上方的绝缘间隔物，并且在所述沟槽中设置第二导电填充物作为所述栅电极的上部。

公开(公告)号：US07141845B2

公开(公告)日：2006-11-28

申请号：US10898706

申请日：2004-07-23

申请人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

发明人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

IPC分类号： H01L27/108

CPC分类号： H01L27/10867 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.

摘要翻译： 每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。 通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏​​极电容的减小以及栅电极和漏电极之间的漏电流 较低的源极/漏极区域。 用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。 单元晶体管的上源/漏区通过接触孔注入而形成。

公开(公告)号：US20060076602A1

公开(公告)日：2006-04-13

申请号：US11222273

申请日：2005-09-08

申请人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Schwerin ,  Till Schloesser ,  Rolf Weis

发明人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Schwerin ,  Till Schloesser ,  Rolf Weis

IPC分类号： H01L29/94 ,  H01L21/8244

CPC分类号： H01L27/108 ,  G11C11/404 ,  H01L27/0207 ,  H01L27/10808 ,  H01L27/10829 ,  H01L29/785

摘要： Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.

摘要翻译： 堆叠和沟槽存储单元被提供在DRAM存储单元阵列中。 堆叠和沟槽存储单元布置成形成相同的单元对，每个单元对具有沟槽电容器，堆叠电容器和半导体鳍片，其中形成用于寻址沟槽和堆叠电容器的两个选择晶体管的有源区。 半导体鳍片沿纵向连续布置以形成单元行，并且在这种布置中，在每种情况下都是沟槽电容器彼此间隔开。 相邻的单元行通过沟槽隔离器结构彼此分离，并且相对于彼此相对于单元对的长度的一半偏移。 半导体鳍片被至少两个相对于单元行正交的有源字线交叉，用于寻址在半导体鳍片中实现的选择晶体管。

公开(公告)号：US20060056228A1

公开(公告)日：2006-03-16

申请号：US10939255

申请日：2004-09-10

申请人： Till Schloesser ,  Rolf Weis ,  Ulrike Schwerin

发明人： Till Schloesser ,  Rolf Weis ,  Ulrike Schwerin

IPC分类号： G11C11/24 ,  H01L29/94

CPC分类号： G11C11/404 ,  H01L27/0207 ,  H01L27/10873 ,  H01L27/10879 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7854

摘要： A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically isolated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.

摘要翻译： 公开了晶体管，存储单元阵列和制造晶体管的方法。 在一个实施例中，本发明涉及至少部分地形成在半导体衬底中的晶体管，包括第一和第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域，所述沟道区域是 设置在所述半导体衬底中，以及栅电极，沿着所述沟道区设置并与所述沟道区电隔离，用于控制在所述第一和第二源/漏区之间流动的电流，其中所述沟道区包括 所述通道具有脊的形状，所述脊包括垂直于连接所述第一和第二源极/漏极区的线的横截面中的顶侧和两个侧边，其中所述顶侧设置在所述半导体的表面下方 基板和所述栅电极沿着所述顶侧和所述两个横向侧面设置。

公开(公告)号：US06932916B2

公开(公告)日：2005-08-23

申请号：US10425179

申请日：2003-04-29

申请人： Dirk Manger ,  Hans-Peter Moll ,  Till Schloesser

发明人： Dirk Manger ,  Hans-Peter Moll ,  Till Schloesser

IPC分类号： H01L21/308 ,  H01L21/334 ,  H01L21/762 ,  H01L21/8242 ,  B44C1/22 ,  H01L21/302

CPC分类号： H01L21/3081 ,  H01L21/3083 ,  H01L21/76229 ,  H01L27/1087 ,  H01L29/66181

摘要： A method for etching trenches having different depths on a semiconductor substrate includes providing a mask with first and second openings. The first and second openings are located where corresponding first and second trenches are to be etched. A slow-etch region, made of a slow-etch material, is provided above the substrate at a location corresponding to the second opening. When exposed to a selected etchant, the slow-etch material is etched at a rate less than the rate at which the semiconductor substrate is etched when exposed to the selected etchant.

摘要翻译： 在半导体衬底上蚀刻具有不同深度的沟槽的方法包括：提供具有第一和第二开口的掩模。 第一和第二开口位于相应的第一和第二沟槽将被蚀刻的位置。 在对应于第二开口的位置处，在衬底上方设置由缓蚀刻材料制成的缓蚀刻区域。 当暴露于所选择的蚀刻剂时，以暴露于所选择的蚀刻剂的半导体衬底被蚀刻的速率小的速率蚀刻慢刻蚀材料。

公开(公告)号：US20050040398A1

公开(公告)日：2005-02-24

申请号：US10766902

申请日：2004-01-30

申请人： Bernhard Kowalski ,  Andreas Felber ,  Valentin Rosskopf ,  Juergen Lindolf ,  Till Schloesser ,  Bernd Goebel

发明人： Bernhard Kowalski ,  Andreas Felber ,  Valentin Rosskopf ,  Juergen Lindolf ,  Till Schloesser ,  Bernd Goebel

IPC分类号： G11C29/50 ,  H01L23/58

CPC分类号： G11C29/50016 ,  G11C11/401 ,  G11C29/50 ,  G11C2029/5006

摘要： An integrated circuit arrangement which has vertical FET selection transistors and storage capacitors in each case of a transistor array and of an assigned memory cell array, said storage capacitors being formed vertically into the depth of a substrate in deep trenches a test structure is integrated, which enables a plurality of vertical FET selection transistors with one another by a conductive electrode material embedded in an extended deep trench With a test structure of this type, it is possible to evaluate characteristic values for leakage currents and capacitances at different semiconductor junctions and also between different sections of the integrated circuit arrangement and also to perform reliability stress tests.

摘要翻译： 一种在晶体管阵列和分配的存储单元阵列的每种情况下具有垂直FET选择晶体管和存储电容器的集成电路装置，所述存储电容器垂直形成在深沟槽中的衬底的深度，测试结构被集成， 通过嵌入在扩展深沟槽中的导电电极材料使得多个垂直FET选择晶体管彼此具有这种类型的测试结构，可以评估不同半导体结处的漏电流和电容的特性值，以及不同的 集成电路布置的部分以及执行可靠性压力测试。

公开(公告)号：US06349052B1

公开(公告)日：2002-02-19

申请号：US09660453

申请日：2000-09-12

申请人： Franz Hofmann ,  Till Schloesser

发明人： Franz Hofmann ,  Till Schloesser

IPC分类号： G11C506

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/1203

摘要： A capacitor of a memory cell is produced in a depression (V) in a first substrate (1). The first substrate (1) is connected to a second substrate (2) in such a way that an insulating layer (I) is arranged between them. The second substrate (2) is thinned. A transistor of the memory cell is produced in the second substrate (2). In order to connect the transistor to the capacitor a first trench (G1) is produced, which trench cuts through the insulating layer (I). By means of isotropic etching, part of the insulating layer (I) which is arranged between the transistor and the capacitor is removed and replaced by a contact (K).

摘要翻译： 在第一衬底（1）中的凹陷（V）中产生存储器单元的电容器。 第一基板（1）以这样的方式连接到第二基板（2），使得绝缘层（I）布置在它们之间。 第二基板（2）变薄。 在第二基板（2）中产生存储单元的晶体管。 为了将晶体管连接到电容器，产生第一沟槽（G1），沟槽切穿绝缘层（I）。 通过各向同性蚀刻，排列在晶体管和电容器之间的部分绝缘层（I）被接触（K）代替。

公开(公告)号：US09825170B2

公开(公告)日：2017-11-21

申请号：US15040624

申请日：2016-02-10

申请人： Franz Hirler ,  Andreas Meiser ,  Till Schloesser

发明人： Franz Hirler ,  Andreas Meiser ,  Till Schloesser

IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L21/765 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L21/265 ,  H01L29/417

CPC分类号： H01L29/7823 ,  H01L21/26586 ,  H01L21/765 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

摘要： A semiconductor device formed in a semiconductor substrate having a first main surface comprises a transistor array and a termination region. The transistor array comprises a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region. The gate electrode is disposed in first trenches. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a first ridge extending along the first direction. The termination region comprises a termination trench, a portion of the termination trench extending in the first direction, a length of the termination trench being larger than a length of the first trenches, the length being measured along the first direction.

公开(公告)号：US07763513B2

公开(公告)日：2010-07-27

申请号：US11222540

申请日：2005-09-09

申请人： Peng-Fei Wang ,  Joachim Nuetzel ,  Rolf Weis ,  Till Schloesser ,  Marc Strasser ,  Hannes Luyken

发明人： Peng-Fei Wang ,  Joachim Nuetzel ,  Rolf Weis ,  Till Schloesser ,  Marc Strasser ,  Hannes Luyken

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L21/28114 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/78

摘要： A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.

摘要翻译： 公开了制造晶体管的方法。 该方法包括形成第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道和用于控制沟道的导电性的栅电极。 栅极通过在衬底中限定栅极沟槽并且在与沟槽相邻的位置处在每个隔离沟槽中限定一个凹穴形成，使得两个凹穴将与凹槽连接，凹槽设置在两个凹槽之间 口袋 栅极绝缘材料设置在有源区域和凹槽之间的界面处以及在有源区域和凹穴之间的界面处。 沉积栅电极材料以填充凹槽和两个凹穴。