公开(公告)号：US20160240661A1

公开(公告)日：2016-08-18

申请号：US15040624

申请日：2016-02-10

申请人： Andreas Meiser ,  Franz Hirler ,  Till Schloesser

发明人： Andreas Meiser ,  Franz Hirler ,  Till Schloesser

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/7823 ,  H01L21/26586 ,  H01L21/765 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

摘要： A semiconductor device formed in a semiconductor substrate having a first main surface comprises a transistor array and a termination region. The transistor array comprises a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region. The gate electrode is disposed in first trenches. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a first ridge extending along the first direction. The termination region comprises a termination trench, a portion of the termination trench extending in the first direction, a length of the termination trench being larger than a length of the first trenches, the length being measured along the first direction.

摘要翻译： 形成在具有第一主表面的半导体衬底中的半导体器件包括晶体管阵列和端接区域。 晶体管阵列包括源区域，漏极区域，体区域，漂移区域和在体区域处的栅电极。 栅极被配置为控制在体区中形成的通道的导电性。 栅电极设置在第一沟槽中。 主体区域和漂移区域沿着源极区域和漏极区域之间的第一方向设置，第一方向平行于第一主表面。 身体区域具有沿着第一方向延伸的第一脊的形状。 端接区域包括端接沟槽，端接沟槽的一部分沿第一方向延伸，端接沟槽的长度大于第一沟槽的长度，该长度沿第一方向被测量。

公开(公告)号：US09825170B2

公开(公告)日：2017-11-21

申请号：US15040624

申请日：2016-02-10

申请人： Franz Hirler ,  Andreas Meiser ,  Till Schloesser

发明人： Franz Hirler ,  Andreas Meiser ,  Till Schloesser

IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L21/765 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L21/265 ,  H01L29/417

CPC分类号： H01L29/7823 ,  H01L21/26586 ,  H01L21/765 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

摘要： A semiconductor device formed in a semiconductor substrate having a first main surface comprises a transistor array and a termination region. The transistor array comprises a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region. The gate electrode is disposed in first trenches. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a first ridge extending along the first direction. The termination region comprises a termination trench, a portion of the termination trench extending in the first direction, a length of the termination trench being larger than a length of the first trenches, the length being measured along the first direction.

公开(公告)号：US08546875B1

公开(公告)日：2013-10-01

申请号：US13420076

申请日：2012-03-14

申请人： Franz Hirler ,  Andreas Meiser

发明人： Franz Hirler ,  Andreas Meiser

IPC分类号： H01L29/40

CPC分类号： H01L29/7811 ,  H01L23/481 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： Described herein are embodiments of a vertical power transistor having drain and gate terminals located on the same side of a semiconductor body and capable of withstanding high voltages in the off-state, in particular voltages of more than 100V.

摘要翻译： 这里描述的是垂直功率晶体管的实施例，其具有位于半导体本体的相同侧上的漏极和栅极端子，并且能够承受处于断开状态的高电压，特别是大于100V的电压。

公开(公告)号：US20130234145A1

公开(公告)日：2013-09-12

申请号：US13413315

申请日：2012-03-06

申请人： Franz Hirler ,  Andreas Meiser

发明人： Franz Hirler ,  Andreas Meiser

IPC分类号： H01L29/20 ,  H01L21/20

CPC分类号： H01L27/095 ,  H01L21/265 ,  H01L21/76283 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/045 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/7787 ,  H01L29/78

摘要： A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials are arranged adjacent one another in a common plane.

公开(公告)号：US09111764B2

公开(公告)日：2015-08-18

申请号：US13548266

申请日：2012-07-13

申请人： Franz Hirler ,  Andreas Meiser ,  Steffen Thiele

发明人： Franz Hirler ,  Andreas Meiser ,  Steffen Thiele

IPC分类号： H03K17/687 ,  H01L27/06 ,  H01L27/082 ,  H01L27/088 ,  H01L29/423 ,  H01L29/40 ,  H01L29/732 ,  H01L29/735 ,  H01L29/78 ,  H01L29/06 ,  H01L23/48

CPC分类号： H01L27/0623 ,  H01L23/481 ,  H01L23/528 ,  H01L27/0826 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42372 ,  H01L29/7327 ,  H01L29/735 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/781 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7824 ,  H01L2924/0002 ,  H03K17/687 ,  H03K19/018507 ,  H03K2217/0063 ,  H03K2217/0072 ,  H03K2217/0081 ,  H01L2924/00

摘要： A bridge circuit is provided. The bridge circuit includes a first integrated semiconductor device having a high-side switch, a second integrated semiconductor device having a low-side switch electrically connected with the high-side switch, a first level-shifter electrically connected with the high-side switch and integrated in one of the first integrated semiconductor device and the second integrated semiconductor device, and a second level-shifter electrically connected with the low-side switch and integrated in one of the first integrated semiconductor device and the second integrated semiconductor device. Further, an integrated semiconductor device is provided.

摘要翻译： 提供了桥接电路。 桥电路包括具有高侧开关的第一集成半导体器件，具有与高侧开关电连接的低侧开关的第二集成半导体器件，与高侧开关电连接的第一电平移位器和 集成在第一集成半导体器件和第二集成半导体器件中的一个中，以及与低侧开关电连接并集成在第一集成半导体器件和第二集成半导体器件中的一个中的第二电平转换器。 此外，提供了集成半导体器件。

公开(公告)号：US20140015586A1

公开(公告)日：2014-01-16

申请号：US13548266

申请日：2012-07-13

申请人： Franz Hirler ,  Andreas Meiser ,  Steffen Thiele

发明人： Franz Hirler ,  Andreas Meiser ,  Steffen Thiele

IPC分类号： H03L5/00

CPC分类号： H01L27/0623 ,  H01L23/481 ,  H01L23/528 ,  H01L27/0826 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42372 ,  H01L29/7327 ,  H01L29/735 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/781 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7824 ,  H01L2924/0002 ,  H03K17/687 ,  H03K19/018507 ,  H03K2217/0063 ,  H03K2217/0072 ,  H03K2217/0081 ,  H01L2924/00

摘要： A bridge circuit is provided. The bridge circuit includes a first integrated semiconductor device having a high-side switch, a second integrated semiconductor device having a low-side switch electrically connected with the high-side switch, a first level-shifter electrically connected with the high-side switch and integrated in one of the first integrated semiconductor device and the second integrated semiconductor device, and a second level-shifter electrically connected with the low-side switch and integrated in one of the first integrated semiconductor device and the second integrated semiconductor device. Further, an integrated semiconductor device is provided.

摘要翻译： 提供了桥接电路。 桥电路包括具有高侧开关的第一集成半导体器件，具有与高侧开关电连接的低侧开关的第二集成半导体器件，与高侧开关电连接的第一电平移位器和 集成在第一集成半导体器件和第二集成半导体器件中的一个中，以及与低侧开关电连接并集成在第一集成半导体器件和第二集成半导体器件中的一个中的第二电平转换器。 此外，提供了集成半导体器件。

公开(公告)号：US09401355B2

公开(公告)日：2016-07-26

申请号：US13328371

申请日：2011-12-16

申请人： Joachim Weyers ,  Anton Mauder ,  Franz Hirler ,  Andreas Meiser ,  Ulrich Glaser

发明人： Joachim Weyers ,  Anton Mauder ,  Franz Hirler ,  Andreas Meiser ,  Ulrich Glaser

IPC分类号： H01L29/66 ,  H01L29/02 ,  H01L23/62 ,  H01L27/06 ,  H01L29/861 ,  H01L27/08 ,  H01L27/02

CPC分类号： H01L27/0255 ,  H01L27/06 ,  H01L27/0814 ,  H01L29/407 ,  H01L29/861 ,  H01L29/8611 ,  H01L29/8725

摘要： One embodiment of an integrated circuit includes a semiconductor body. In the semiconductor body a first trench region extends into the semiconductor body from a first surface. The integrated circuit further includes a diode including an anode region and a cathode region. One of the anode region and the cathode region is at least partly arranged in the first trench region. The other one of the anode region and the cathode region includes a first semiconductor region adjoining the one of the anode region and the cathode region from outside of the first trench region.

摘要翻译： 集成电路的一个实施例包括半导体本体。 在半导体本体中，第一沟槽区域从第一表面延伸到半导体本体中。 集成电路还包括包括阳极区域和阴极区域的二极管。 阳极区域和阴极区域中的一个至少部分地布置在第一沟槽区域中。 阳极区域和阴极区域中的另一个包括从第一沟槽区域的外部邻接阳极区域和阴极区域中的一个的第一半导体区域。

公开(公告)号：US08916909B2

公开(公告)日：2014-12-23

申请号：US13413315

申请日：2012-03-06

申请人： Franz Hirler ,  Andreas Meiser

发明人： Franz Hirler ,  Andreas Meiser

IPC分类号： H01L29/739

CPC分类号： H01L27/095 ,  H01L21/265 ,  H01L21/76283 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/092 ,  H01L29/045 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/7787 ,  H01L29/78

摘要： A semiconductor device is disclosed. In one embodiment, the semiconductor device includes two different semiconductor materials. The two semiconductor materials are arranged adjacent one another in a common plane.

摘要翻译： 公开了一种半导体器件。 在一个实施例中，半导体器件包括两种不同的半导体材料。 两个半导体材料在公共平面中彼此相邻布置。

公开(公告)号：US08871573B2

公开(公告)日：2014-10-28

申请号：US13547339

申请日：2012-07-12

申请人： Franz Hirler ,  Andreas Meiser

发明人： Franz Hirler ,  Andreas Meiser

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/739 ,  H01L29/732 ,  H01L23/48 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/732 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/481 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/42304 ,  H01L29/42372 ,  H01L29/66272 ,  H01L29/66295 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7815 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device is provided. The method includes providing a wafer-stack having a main horizontal surface, an opposite surface, a buried dielectric layer, a semiconductor wafer extending from the buried dielectric layer to the main horizontal surface, and a handling wafer extending from the buried dielectric layer to the opposite surface; etching a deep vertical trench into the semiconductor wafer at least up to the buried dielectric layer, wherein the buried dielectric layer is used as an etch stop; forming a vertical transistor structure comprising forming a first doped region in the semiconductor wafer; forming a first metallization on the main horizontal surface in ohmic contact with the first doped region; removing the handling wafer to expose the buried dielectric layer; and masked etching of the buried dielectric layer to partly expose the semiconductor wafer on a back surface opposite to the main horizontal surface.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括提供具有主水平表面，相对表面，埋入介质层，从掩埋介电层延伸到主水平表面的半导体晶片的晶片堆叠，以及从掩埋介电层延伸到 对面 将深的垂直沟槽蚀刻到至少直到埋入的介电层的半导体晶片内，其中埋入的介电层用作蚀刻停止层; 形成垂直晶体管结构，包括在半导体晶片中形成第一掺杂区; 在所述主水平表面上与所述第一掺杂区域欧姆接触形成第一金属化; 去除所述处理晶片以暴露所述埋入的介电层; 以及掩埋的介电层的掩模蚀刻以在与主水平表面相对的背面部分地暴露半导体晶片。

公开(公告)号：US20130005099A1

公开(公告)日：2013-01-03

申请号：US13537374

申请日：2012-06-29

申请人： Hans Weber ,  Franz Hirler ,  Andreas Meiser ,  Anton Mauder ,  Kurt Sorschag ,  Stefan Gamerith ,  Roman Knoefler

发明人： Hans Weber ,  Franz Hirler ,  Andreas Meiser ,  Anton Mauder ,  Kurt Sorschag ,  Stefan Gamerith ,  Roman Knoefler

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L29/7802 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0629 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7828

摘要： A semiconductor device with a dielectric layer is produced by providing a semiconductor body with a first trench extending into the semiconductor body, the first trench having a bottom and a sidewall. A first dielectric layer is formed on the sidewall in a lower portion of the first trench and a first plug is formed in the lower portion of the first trench so as to cover the first dielectric layer. The first plug leaves an upper portion of the sidewall uncovered. A sacrificial layer is formed on the sidewall in the upper portion of the first trench and a second plug is formed in the upper portion of the first trench. The sacrificial layer is removed so as to form a second trench having sidewalls and a bottom. A second dielectric layer is formed in the second trench and extends to the first dielectric layer.

摘要翻译： 具有电介质层的半导体器件通过向半导体本体提供延伸到半导体本体中的第一沟槽，第一沟槽具有底部和侧壁来制造。 第一电介质层形成在第一沟槽的下部的侧壁上，第一插塞形成在第一沟槽的下部，以覆盖第一电介质层。 第一个塞子留下未覆盖的侧壁的上部。 牺牲层形成在第一沟槽的上部的侧壁上，第二插塞形成在第一沟槽的上部。 除去牺牲层以形成具有侧壁和底部的第二沟槽。 第二介电层形成在第二沟槽中并延伸到第一介电层。