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公开(公告)号：US4074353A
公开(公告)日：1978-02-14
申请号：US689014
申请日：1976-05-24
CPC分类号： G06F9/462
摘要： A plurality of trap save areas are linked to form a pool of such areas from which an area may be loaded with context from various sources in response to a trap condition, such as the addressing of unuseable memory, the loaded area unlinked from the pool, and various pointers changed to reflect such unlinking. The unlinked area is associated with the process which was executing at the time of the occurrence of the trap condition by effectively being coupled to the interrupt level of such process. Independent of the interrupt level, a trap handler routine, specific to the nature of the trap condition, is executed following which the unlinked area is returned to the pool and the various pointers changed to reflect such return.
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32.发明授权Microprogrammed control of extended integer and commercial instruction processor instructions through use of a data type field in a central processor unit 失效通过使用中央处理器单元中的数据类型字段对扩展整数和商业指令处理器指令进行微编程控制
公开(公告)号：US4491908A
公开(公告)日：1985-01-01
申请号：US326442
申请日：1981-12-01
CPC分类号： G06F9/30192 , G06F9/26 , G06F9/268
摘要： A data processing system includes a microprogram controlled central processing unit that executes instructions. The instruction words include a data type field for identifying the type of operand processed during the execution of the instruction. The data type field signals and a number of control signals are applied to the address terminals of a read only memory. The read only memory output signals are tested by microwords of a microprogram to branch to firmware routines to process the operand type.
摘要翻译： 数据处理系统包括执行指令的微程序控制的中央处理单元。 指令字包括用于识别在执行指令期间处理的操作数的类型的数据类型字段。 数据类型场信号和多个控制信号被施加到只读存储器的地址端子。 只读存储器输出信号由微程序的微字测试以分支到固件例程以处理操作数类型。
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公开(公告)号：US4348723A
公开(公告)日：1982-09-07
申请号：US140642
申请日：1980-04-15
CPC分类号： G06F9/267
摘要： A first bank or a second bank of storage locations of a control store of a data processing system is enabled in response to one of a plurality of test signals received as parallel inputs by two multiplexer devices. Only one of the multiplexers is enabled at a given time in response to the polarity of one of the test signals selected from the inputs of the multiplexer devices.
摘要翻译： 响应于由两个多路复用器装置作为并行输入接收的多个测试信号中的一个启用数据处理系统的控制存储器的第一存储体或第二存储区域。 响应于从多路复用器装置的输入中选择的一个测试信号的极性，在给定时间只有一个复用器被使能。
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公开(公告)号：US4320455A
公开(公告)日：1982-03-16
申请号：US100028
申请日：1979-12-03
CPC分类号： G06F9/4881 , G06F9/546
摘要： One or more queue structures in a data processing system may include a threaded list of frames which are enqueued or dequeued from the list in accordance with four instructions wherein each list is tied to a so-called lock or control frame with synchronization for multiple processing units. Multiple lock frames and accordingly multiple lists of frames may be coupled in the system for the purpose of accomplishing the various tasks necessary.
摘要翻译： 数据处理系统中的一个或多个队列结构可以包括根据四个指令从列表排队或出队的帧的线程列表，其中每个列表被绑定到所谓的锁定或控制帧，具有多个处理单元的同步 。 多个锁帧和相应的多个帧列表可以耦合在系统中以实现所需的各种任务。
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公开(公告)号：US4363095A
公开(公告)日：1982-12-07
申请号：US221851
申请日：1980-12-31
申请人： William E. Woods , Arthur Peters
发明人： William E. Woods , Arthur Peters
CPC分类号： G06F12/0851
摘要： In a data processing system a cache memory comprises level one and level two even and odd data stores and level one and level two even and odd directory stores. The directory stores include a plurality of storage locations for storing the most significant bits of the address numbers associated with the data words stored in the level one and level two even and odd data stores. The level one and level two even and odd directory stores are addressed by the least significant bits of the address numbers. Comparator circuits compare the high order bits of an address number supplied in a memory request to the high order bits stored in the level one even and odd directory stores at storage locations identified by both the low order bits of the address supplied in the memory request and the low order address bits incremented by one. A hit detector circuit determines whether one, both, or none of the requested words are stored in the cache memory by analyzing the outputs of the comparators.
摘要翻译： 在数据处理系统中，高速缓冲存储器包括一级和二级偶数和奇数数据存储，以及一级和二级偶数和奇数目录存储。 目录存储包括用于存储与存储在一级和二级偶数和奇数数据存储中的数据字相关联的地址号的最高有效位的多个存储位置。 一级和二级偶数和奇数目录存储由地址号的最低有效位寻址。 比较器电路将存储器请求中提供的地址号码的高位比较与存储在一级偶数和奇数目录中的高位比特存储在由存储器请求中提供的地址的低位比特识别的存储位置处， 低位地址位递增1。 命中检测器电路通过分析比较器的输出来确定所请求的字中的一个，两个，还是没有一个被存储在高速缓冲存储器中。
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公开(公告)号：US4799181A
公开(公告)日：1989-01-17
申请号：US913810
申请日：1986-09-30
申请人： Steven A. Tague , William E. Woods
发明人： Steven A. Tague , William E. Woods
摘要： A binary arithmetic unit performs arithmetic operations on binary coded decimal (BCD) operands by converting the BCD digits to hexadecimal excess 3 digits, generating hexadecimal excess 6 partial product digits and modifying selected excess 6 partial product digits to generate a BCD result.
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公开(公告)号：US5442866A
公开(公告)日：1995-08-22
申请号：US903356
申请日：1992-06-24
申请人： William E. Woods
发明人： William E. Woods
IPC分类号： G01B3/10
CPC分类号： G01C15/06 , G01B3/1071 , G01B2003/1074
摘要： An assembly for use by a surveyor having a ruler and an apparatus for securing the ruler to a surveyor's pole. The ruler has a retractable tape and a belt clip. The apparatus for securing the ruler to a pole includes a cradle sized to retain the ruler, a stop member, a planar wall member and attachment members for securing the apparatus to a pole. By securing the ruler to a pole, a single person may complete measurements which previously required two people. The tape of the ruler includes measurements which are inverted with respect to the tenth of a foot for easier reading.
摘要翻译： 由具有标尺的测量员使用的组件和用于将标尺固定在测量仪杆上的装置。 尺子有一个伸缩带和一个皮带夹。 用于将标尺固定到杆上的装置包括：尺寸设置成保持标尺的支架，止动构件，平面壁构件和用于将装置固定到杆上的附接构件。 通过将标尺固定在杆上，单个人可以完成以前需要两个人的测量。 标尺的磁带包括相对于十分之一英尺反转的测量，以便于阅读。
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公开(公告)号：US5243601A
公开(公告)日：1993-09-07
申请号：US593411
申请日：1990-10-05
申请人： Steven A. Tague , William E. Woods
发明人： Steven A. Tague , William E. Woods
CPC分类号： G06F11/28 , G06F11/0721 , G06F11/0751 , G06F11/0793 , G06F11/0763 , G06F2201/86 , G06F2201/865
摘要： A method and apparatus pertaining to a firmware control unit for detecting when such control unit is not behaving properly. The control unit is organized to include in each location of the unit's control store, to which control is not expected to transfer, a predetermined type of pattern containing an address specifying the address of that location, a suitable tag identifying the probable reason for the unexplained jump, and a transfer of control to the appropriate entry point in a reporting firmware routine within the control store. The reporting firmware routine has a number of entry points for collecting all the executions of unexpected locations and for storing the appropriate address and tag information in a predetermined register file for later referencing by an unusual event (UEV) handler routine.
摘要翻译： 一种固件控制单元的方法和装置，用于检测这种控制单元何时不能正常地运行。 控制单元被组织成包括在单元的控制存储器的每个位置，对于哪个控制不期望传送，包含指定该位置的地址的地址的预定类型的模式，标识不明原因的可能原因的合适标签 跳转，以及将控制权转移到控制商店内的报告固件例程中的适当入口点。 报告固件程序具有多个入口点，用于收集意外位置的所有执行，并将适当的地址和标签信息存储在预定的寄存器文件中，以便稍后通过异常事件（UEV）处理程序引用。
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公开(公告)号：US5515525A
公开(公告)日：1996-05-07
申请号：US128391
申请日：1993-09-28
CPC分类号： G06F9/45537 , G06F12/109
摘要： A memory translation mechanism and method executing in a second system to perform first system memory operations for first system executive and user tasks executing on the second system which includes a second system memory organized as a plurality of memory segments, wherein first memory segments are designated to correspond to system memory areas and second memory segments are designated to correspond to user memory areas, and wherein each memory segment corresponds to a combination of a type of first system task and a type of a first system memory area. An interpreter maps by reading an identification of the type of the task corresponding to the first system virtual address from the task type memory and the area type value from the first system virtual address and determining a memory segment corresponding to the type of the first system task and the type of first system area referenced by the first system virtual address. The interpreter maps the identified segment to a memory pool identifier wherein each memory pool identifier corresponds to a task. The second system includes a plurality of pseudo device drivers corresponding to first system input/output devices. Each pseudo device driver includes a segment mapping mechanism which includes a segment pool for storing entries relating memory pool identifiers and providing a corresponding base address identifying the location of the corresponding memory segment in the second system memory.
摘要翻译： 一种在第二系统中执行的存储器转换机制和方法，用于对第二系统执行第一系统执行和用户任务执行第一系统存储器操作，所述第二系统执行和用户任务包括被组织为多个存储器段的第二系统存储器，其中第一存储器段被指定为 对应于系统存储器区域，并且第二存储器段被指定为对应于用户存储区域，并且其中每个存储器段对应于第一系统任务的类型和第一系统存储器区域的类型的组合。 解释器通过从任务类型存储器读取对应于第一系统虚拟地址的任务的类型的标识和来自第一系统虚拟地址的区域类型值来映射，并且确定对应于第一系统任务的类型的存储器段 以及由第一个系统虚拟地址引用的第一个系统区域的类型。 解释器将所识别的片段映射到存储器池标识符，其中每个存储器池标识符对应于任务。 第二系统包括对应于第一系统输入/输出装置的多个伪装置驱动器。 每个伪设备驱动器包括段映射机制，其包括用于存储与存储器池标识符相关的条目的段池，并且提供标识第二系统存储器中对应的存储器段的位置的相应基地址。
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公开(公告)号：US4432050A
公开(公告)日：1984-02-14
申请号：US192875
申请日：1980-10-01
CPC分类号： G06F9/24
摘要： Use of a control storage device coupled with a central processing unit is locked, during the loading process from the unit to the device, to a would-be user of the device until such loading process is complete as indicated by a so-called "unlock" command received from the central processing unit. An indication of an error or malfunction in the control storage device either during the loading process or thereafter is also provided to the central processing unit.
摘要翻译： 在从单元到设备的装载过程中，与中央处理单元耦合的控制存储设备的使用被锁定，直到这种加载过程完成为止，如所谓的“解锁 “命令从中央处理单元收到。 控制存储设备中的错误或故障的指示在加载过程中或之后也被提供给中央处理单元。
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