公开(公告)号：US09263522B2

公开(公告)日：2016-02-16

申请号：US14100760

申请日：2013-12-09

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  PR Chidambaram

IPC: H01L29/15 ,  H01L29/10 ,  H01L29/205 ,  H01L29/66 ,  H01L21/74 ,  H01L29/78

CPC classification number: H01L29/1045 ,  H01L21/743 ,  H01L29/1054 ,  H01L29/1087 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: An apparatus comprises a substrate. The apparatus also comprises a diffusion barrier formed on a surface of a first region of the substrate. The diffusion barrier is formed using a first material having a first band gap energy. The apparatus further comprises a channel region formed on a surface of the diffusion barrier. The channel region is formed using a second material having a second band gap energy that is lower than the first band gap energy. The apparatus further comprises a back gate contact coupled to the first region of the substrate.

Abstract translation: 一种装置包括基板。 该装置还包括形成在基板的第一区域的表面上的扩散阻挡层。 使用具有第一带隙能量的第一材料形成扩散阻挡层。 该装置还包括形成在扩散阻挡层的表面上的沟道区。 沟道区域使用具有低于第一带隙能量的第二带隙能量的第二材料形成。 该装置还包括耦合到衬底的第一区域的背栅极接触。

公开(公告)号：US09203013B2

公开(公告)日：2015-12-01

申请号：US13872338

申请日：2013-04-29

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung H. Kang ,  Xiaochun Zhu

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  G11C11/15

CPC classification number: H01L43/02 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: An apparatus includes a structure that includes a bottom cap layer surrounding a metal pad. The apparatus also includes a magnetic tunnel junction (MTJ) device that includes a bottom electrode coupled to the structure. The MTJ device includes magnetic tunnel junction layers, a top electrode, and a logic cap layer. The MTJ device is offset with respect to the metal pad.

Abstract translation: 一种装置包括包括围绕金属垫的底盖层的结构。 该装置还包括磁隧道结（MTJ）装置，其包括耦合到该结构的底部电极。 MTJ装置包括磁性隧道结层，顶部电极和逻辑帽层。 MTJ装置相对于金属垫偏移。

公开(公告)号：US20150340101A1

公开(公告)日：2015-11-26

申请号：US14820101

申请日：2015-08-06

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Xiaochun Zhu

IPC: G11C17/08

CPC classification number: G11C17/08 ,  G11C7/00 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C17/16 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/10802 ,  H01L29/7841

Abstract: A method includes applying a programming voltage to a drain of an access transistor, where a source of the access transistor is coupled to a drain region of a one-time programmable (OTP) device. The method also includes applying a first voltage to a gate of the OTP device and a second voltage to a terminal of the OTP device to bias a channel region of the OTP device, where the first voltage and the second voltage are substantially equal.

Abstract translation: 一种方法包括将编程电压施加到存取晶体管的漏极，其中存取晶体管的源极耦合到一次可编程（OTP）器件的漏极区。 该方法还包括将第一电压施加到OTP器件的栅极，并将第二电压施加到OTP器件的端子以偏置OTP器件的沟道区域，其中第一电压和第二电压基本相等。

公开(公告)号：US09153587B2

公开(公告)日：2015-10-06

申请号：US14659893

申请日：2015-03-17

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Stanley Seungchul Song

IPC: H01L21/336 ,  H01L29/786 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/265 ,  G06F17/50

CPC classification number: H01L27/0924 ,  G06F17/5045 ,  G06F17/5068 ,  H01L21/265 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0607 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin-type semiconductor device comprises means for providing a first fin-type conduction channel having first and second regions, means for providing a second fin-type conduction channel having a fourth region above a third region, and means for shielding current leakage coupled to at least one of the first region and the third region. The first region has a first doping concentration greater than a second doping concentration of the second region. The first fin-type conduction channel comprises first ion implants implanted into the substrate at a first depth and second ion implants implanted into the substrate at a different depth. The third region has a third doping concentration, and the fourth region has a fourth doping concentration.

Abstract translation: 一种装置包括从衬底延伸的衬底和鳍式半导体器件。 翅片型半导体器件包括用于提供具有第一和第二区域的第一鳍式传导沟道的装置，用于提供具有在第三区域上方的第四区域的第二鳍式传导沟道的装置，以及用于屏蔽漏电耦合到 第一区域和第三区域中的至少一个。 第一区域具有大于第二区域的第二掺杂浓度的第一掺杂浓度。 第一鳍型传导通道包括在第一深度处植入衬底中的第一离子植入物和在不同深度处植入衬底中的第二离子植入物。 第三区域具有第三掺杂浓度，第四区域具有第四掺杂浓度。

公开(公告)号：US20150145592A1

公开(公告)日：2015-05-28

申请号：US14225836

申请日：2014-03-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Daeik Daniel Kim ,  Bin Yang ,  Jonghae Kim ,  Daniel Wayne Perry

IPC: H01L29/739 ,  G05F3/16

CPC classification number: H01L29/7393 ,  G05F3/16 ,  H01L27/0705

Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.

Abstract translation: 一种方法包括根据场效应晶体管（FET）型操作，偏置第一栅极电压以使单相电流从晶体管的第一区域流过晶体管的第二区域。 该方法还包括偏置主体端子以使得双极电流能够根据双极结型晶体管（BJT）型操作从第一区域流动到第二区域。 单极电流与双极电流同时流动，在互补金属氧化物半导体（CMOS）技术中提供双模数字和模拟器件。

公开(公告)号：US08969984B2

公开(公告)日：2015-03-03

申请号：US14048704

申请日：2013-10-08

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Seung Hyuk Kang ,  Xia Li ,  Kangho Lee

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetic tunnel junction device includes a Synthetic Anti-Ferromagnetic (SAF) layer, a first free layer, and second free layer. The magnetic tunnel junction device further includes a spacer layer between the first and second free layers. The first free layer is magneto-statically coupled to the second free layer. A thickness of the spacer layer is at least 4 Angstroms.

Abstract translation: 磁性隧道结装置包括合成反铁磁（SAF）层，第一自由层和第二自由层。 磁性隧道结装置还包括在第一和第二自由层之间的间隔层。 第一自由层被磁静态耦合到第二自由层。 间隔层的厚度至少为4埃。

公开(公告)号：US20150056722A1

公开(公告)日：2015-02-26

申请号：US14518459

申请日：2014-10-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Matthew Michael Nowak

IPC: H01L43/12

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack.

Abstract translation: 存储器件可以包括磁性隧道结（MTJ）堆叠，底部电极（BE）层和接触层。 MTJ堆叠可以包括自由层，阻挡层和钉扎层。 BE层可以耦合到MTJ堆叠，并且封装在平坦化层中。 BE层也可以具有与MTJ叠层相当的共同轴。 接触层可以嵌入在BE层中，并且在BE层和MTJ堆叠之间形成界面。

公开(公告)号：US08865481B2

公开(公告)日：2014-10-21

申请号：US14172208

申请日：2014-02-04

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaochun Zhu ,  Seung Hyuk Kang

IPC: H01L29/82 ,  B82Y10/00 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/12 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

Abstract: A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps.

Abstract translation: 半导体器件包括被配置为设置在具有逻辑元件的公共层间金属电介质（IMD）层中的磁隧道结（MTJ）存储元件。 盖层将公共IMD层与顶部和底部IMD层分开。 顶部和底部电极耦合到MTJ存储元件。 金属与电极的连接分别通过分离盖层中的通孔形成在顶部和底部IMD层中。 或者，分离盖层是凹进的并且底部电极被嵌入，从而建立与底部IMD层中的金属连接的直接接触。 通过用金属岛和隔离帽隔离与MTJ存储元件的金属连接来实现与公共IMD层中顶部电极的金属连接。

公开(公告)号：US20140273288A1

公开(公告)日：2014-09-18

申请号：US14294205

申请日：2014-06-03

Applicant: QUALCOMM Incorporated

Inventor： Xia Li

IPC: H01L43/12

CPC classification number: H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/5607 ,  G11C2211/5615 ,  H01F10/3254 ,  H01F41/308 ,  H01L27/222 ,  H01L43/08

Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure.

Abstract translation: 公开了一种形成磁性隧道结装置的方法，其包括在衬底中形成沟槽，沟槽包括多个侧壁和底壁。 所述方法包括在所述沟槽内靠近所述侧壁之一沉积第一导电材料，并在所述沟槽内沉积第二导电材料。 该方法还包括沉积材料以在沟槽内形成磁隧道结（MTJ）结构。 MTJ结构包括具有固定磁性取向的磁场的固定磁性层，隧道结层和具有可配置磁性取向的磁场的自由磁性层。 该方法还包括选择性地移除MTJ结构的一部分以在MTJ结构中形成开口。

公开(公告)号：US20140231940A1

公开(公告)日：2014-08-21

申请号：US13770306

申请日：2013-02-19

Applicant: QUALCOMM INCORPORATED

Inventor： William H. Xia ,  Wenqing Wu ,  Kendrick H. Yuen ,  Abhishek Banerjee ,  Xia Li ,  Seung H. Kang ,  Jung Pill Kim

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  H01L43/08 ,  H01L43/12

Abstract: A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current.

Abstract translation: 存储单元包括耦合到磁隧道结（MTJ）结构的细长第一电极和与耦合到MTJ结构的细长第一电极对准的细长第二电极。 细长电极被配置为引导开关电流感应磁场的相互添加部分通过MTJ。 响应于开关电流的应用，相互添加的部分增强MTJ的切换。