公开(公告)号：US20070284674A1

公开(公告)日：2007-12-13

申请号：US11423286

申请日：2006-06-09

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Kathryn T. Schonenberg ,  Thomas A. Wallner

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Kathryn T. Schonenberg ,  Thomas A. Wallner

IPC分类号： H01L29/94

CPC分类号： H01L29/16 ,  H01L29/66242 ,  H01L29/7371

摘要： A method of forming an isolation region using porous silicon and a related structure are disclosed. One embodiment of the method may include forming a collector region; forming a porous silicon region in the collector region; forming a crystalline silicon intrinsic base layer over the collector region, the intrinsic base layer extending over a portion of the porous silicon region to form an extrinsic base; and forming an isolation region in the porous silicon region. The method is applicable to forming an HBT having a structure including a crystalline silicon intrinsic base extending beyond a collector region and extending over an isolation region to form a continuous intrinsic-to-extrinsic base conduction path of low resistance. The HBT has improved performance by having a smaller collector to intrinsic base interface and larger intrinsic base to extrinsic base interface.

摘要翻译： 公开了使用多孔硅形成隔离区域的方法和相关结构。 该方法的一个实施例可以包括形成收集区域; 在集电区域形成多孔硅区域; 在所述集电极区上形成晶体硅本征基极层，所述本征基极层在所述多孔硅区域的一部分上延伸以形成外部基极; 以及在所述多孔硅区域中形成隔离区域。 该方法适用于形成具有包括结晶硅本征基底的结构的HBT，该晶体硅本征基极延伸超过集电极区域并在隔离区域上延伸以形成具有低电阻的连续本征至外在的基极传导路径。 HBT通过使内部基本接口具有较小的集电极和较大的内在基极到外部基极接口来提高性能。

公开(公告)号：US07119416B1

公开(公告)日：2006-10-10

申请号：US11169444

申请日：2005-06-29

申请人： Thomas N. Adam ,  Kevin K. Chan ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu ,  Beth Ann Rainey ,  Kathryn T. Schonenberg

发明人： Thomas N. Adam ,  Kevin K. Chan ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu ,  Beth Ann Rainey ,  Kathryn T. Schonenberg

IPC分类号： H01L27/82 ,  H01L29/70

CPC分类号： H01L29/7378 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287

摘要： The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

公开(公告)号：US06982442B2

公开(公告)日：2006-01-03

申请号：US10707712

申请日：2004-01-06

申请人： Kevin K. Chan ,  Marwan H. Khater ,  Kathryn T. Schonenberg ,  Panda Siddhartha

发明人： Kevin K. Chan ,  Marwan H. Khater ,  Kathryn T. Schonenberg ,  Panda Siddhartha

IPC分类号： H01L29/737

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

摘要： A heterojunction bipolar transistor (HBT) and method of making an HBT are provided. The HBT includes a collector, and an intrinsic base overlying the collector. The intrinsic base includes a layer of a single-crystal semiconductor alloy. The HBT further includes a raised extrinsic base having a first semiconductive layer overlying the intrinsic base and a second semiconductive layer formed on the first semiconductive layer. An emitter overlies the intrinsic base, and is disposed in an opening of the first and second semiconductive layers, such that the raised extrinsic base is self-aligned to the emitter.

摘要翻译： 提供异质结双极晶体管（HBT）和制造HBT的方法。 HBT包括收集器和覆盖收集器的本征基极。 本征基底包括一层单晶半导体合金。 HBT还包括凸起的非本征基底，其具有覆盖本征基底的第一半导体层和形成在第一半导体层上的第二半导体层。 发射极覆盖本征基极，并且设置在第一和第二半导体层的开口中，使得凸出的外基极与发射极自对准。

公开(公告)号：US06869852B1

公开(公告)日：2005-03-22

申请号：US10707756

申请日：2004-01-09

申请人： Alvin J. Joseph ,  Qizhi Liu ,  BethAnn Rainey ,  Kathryn T. Schonenberg

发明人： Alvin J. Joseph ,  Qizhi Liu ,  BethAnn Rainey ,  Kathryn T. Schonenberg

IPC分类号： H01L21/331 ,  H01L29/10 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242

摘要： A method of fabricating a bipolar transistor structure that provides unit current gain frequency (fT) and maximum oscillation frequency (fMAX) improvements of a raised extrinsic base using non-self-aligned techniques to establish a self-aligned structure. Accordingly, the invention eliminates the complexity and cost of current self-aligned raised extrinsic base processes. The invention forms a raised extrinsic base and an emitter opening over a landing pad, i.e., etch stop layer, then replaces the landing pad with a conductor that is converted, in part, to an insulator. An emitter is then formed in the emitter opening once the insulator is removed from the emitter opening. An unconverted portion of the conductor provides a conductive base link and a remaining portion of the insulator under a spacer isolates the extrinsic base from the emitter while maintaining self-alignment of the emitter to the extrinsic base. The invention also includes the resulting bipolar transistor structure.

摘要翻译： 一种制造双极晶体管结构的方法，其使用非自对准技术建立自对准结构来提供升高的外部基极的单位电流增益频率（fT）和最大振荡频率（fMAX）改善。 因此，本发明消除了当前自对准引起的外在基本过程的复杂性和成本。 本发明形成凸起的非本征基极和在着陆焊盘（即，蚀刻停止层）上开口的发射体，然后用部分转换为绝缘体的导体代替着陆焊盘。 一旦绝缘体从发射极开口移除，就在发射极开口中形成发射极。 导体的未转换部分提供导电基极连接，并且在间隔物下方的绝缘体的剩余部分将外部基极与发射极隔离，同时保持发射极到外部基极的自对准。 本发明还包括所得到的双极晶体管结构。

公开(公告)号：US06844225B2

公开(公告)日：2005-01-18

申请号：US10345469

申请日：2003-01-15

申请人： Huajie Chen ,  Kathryn T. Schonenberg ,  Gregory G. Freeman ,  Andreas D. Stricker ,  Jae-Sung Rieh

发明人： Huajie Chen ,  Kathryn T. Schonenberg ,  Gregory G. Freeman ,  Andreas D. Stricker ,  Jae-Sung Rieh

IPC分类号： H01L21/321 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L21/00

CPC分类号： H01L29/66242 ,  H01L21/32105 ,  Y10S438/911

摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.

摘要翻译： 使用不同材料的不同氧化速率形成自对准氧化物掩模。 自对准氧化物掩模形成在CVD生长的基底NPN基层上，其牺牲了场上的活性区域上的单晶Si（或Si / SiGe）和多晶Si（或Si / SiGe）。 通过利用多晶硅（或Si / SiGe）比单晶Si（或Si / SiGe）更快地氧化的事实来制造自对准掩模。 通过使用热氧化工艺在多晶硅（或Si / siGe）和单晶Si（或Si / siGe）上形成氧化膜，以在多晶硅（或Si / SiGe）上形成厚的氧化层，以及 在单晶Si（或Si / siGe）上方的薄氧化层，随后进行受控氧化物蚀刻以除去单晶Si（或Si / siGe）上的薄氧化层，同时将自对准氧化物掩模层留在 多晶硅（或Si / siGe）。 然后在自对准掩模形成之后形成隆起的外在基体。 该自对准氧化物掩模阻挡从扩展的外在碱基到收集器角的扩散。

公开(公告)号：US06744079B2

公开(公告)日：2004-06-01

申请号：US09683983

申请日：2002-03-08

申请人： Basanth Jagannathan ,  Alvin J. Joseph ,  Xuefeng Liu ,  Kathryn T. Schonenberg ,  Ryan W. Wuthrich

发明人： Basanth Jagannathan ,  Alvin J. Joseph ,  Xuefeng Liu ,  Kathryn T. Schonenberg ,  Ryan W. Wuthrich

IPC分类号： H01L31072

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20% and a boron-doped base region formed therein having a thickness. The base region includes diffusion-limiting impurities substantially throughout its thickness, at a peak concentration below that of boron in the base region. Both the base region and the diffusion-limiting impurities are positioned relative to a peak concentration of Ge in the SiGe layer so as to optimize both performance and yield.

摘要翻译： 具有峰值Ge浓度至少为20％的SiGe层和其中形成有硼掺杂基底区域的高性能SiGe HBT具有厚度。 碱性区域在其整个厚度上基本上包括扩散限制性杂质，峰值浓度低于碱性区域中硼的峰值浓度。 碱性区域和扩散限制杂质都相对于SiGe层中的Ge的峰值浓度定位，以便优化性能和产率。

公开(公告)号：US06534371B2

公开(公告)日：2003-03-18

申请号：US09878605

申请日：2001-06-11

申请人： Douglas D. Coolbaugh ,  Kathryn T. Schonenberg

发明人： Douglas D. Coolbaugh ,  Kathryn T. Schonenberg

IPC分类号： H01L21331

CPC分类号： H01L29/7378 ,  H01L21/26506 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/66242 ,  H01L29/66318

摘要： A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

公开(公告)号：US06448124B1

公开(公告)日：2002-09-10

申请号：US09439067

申请日：1999-11-12

申请人： Douglas D. Coolbaugh ,  James S. Dunn ,  Peter J. Geiss ,  Peter B. Gray ,  David L. Harame ,  Kathryn T. Schonenberg ,  Stephen A. St. Onge ,  Seshadri Subbanna

发明人： Douglas D. Coolbaugh ,  James S. Dunn ,  Peter J. Geiss ,  Peter B. Gray ,  David L. Harame ,  Kathryn T. Schonenberg ,  Stephen A. St. Onge ,  Seshadri Subbanna

IPC分类号： H01L218238

CPC分类号： H01L21/76224 ,  H01L21/763 ,  H01L21/8249

摘要： A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.

摘要翻译： 提供一种形成BiCMOS集成电路的方法，其包括以下步骤：（a）在衬底的第一区域中形成双极器件的第一部分; （b）在所述第一区域上形成第一保护层以保护所述双极器件的所述第一部分; （c）在所述衬底的第二区域中形成场效应晶体管器件; （d）在所述衬底的所述第二区域上形成第二保护层以保护所述场效应晶体管器件; （e）去除所述第一保护层; （f）在所述衬底的所述第一区域中形成所述双极器件的第二部分; 和（g）去除所述第二保护层。

公开(公告)号：US08378424B2

公开(公告)日：2013-02-19

申请号：US13599573

申请日：2012-08-30

申请人： Abhishek Dube ,  Viorel Ontalus ,  Kathryn T. Schonenberg ,  Zhengmao Zhu

发明人： Abhishek Dube ,  Viorel Ontalus ,  Kathryn T. Schonenberg ,  Zhengmao Zhu

IPC分类号： H01L29/66

CPC分类号： H01L21/823425 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/823412 ,  H01L22/12 ,  H01L22/34 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.

摘要翻译： 提供了具有晶体管结构的半导体衬底和在晶体管结构之间具有小于测试结构之间的间隔的测试结构。 第一迭代执行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有掺杂剂的第一浓度的第一掺杂外延层，并蚀刻第一掺杂外延层。 第二迭代进行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有高于第一浓度的掺杂剂的第二浓度的第二掺杂外延层，并蚀刻第二掺杂外延层。 第一个浓度导致超过晶体管结构的第一净增长率，而第二浓度导致比晶体管结构高出测试结构的较低的第二净增长率，导致模式负载减小。

公开(公告)号：US20120319110A1

公开(公告)日：2012-12-20

申请号：US13599573

申请日：2012-08-30

申请人： Abhishek Dube ,  Viorel Ontalus ,  Kathryn T. Schonenberg ,  Zhengmao Zhu

发明人： Abhishek Dube ,  Viorel Ontalus ,  Kathryn T. Schonenberg ,  Zhengmao Zhu

IPC分类号： H01L29/36

CPC分类号： H01L21/823425 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/823412 ,  H01L22/12 ,  H01L22/34 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.

摘要翻译： 提供了具有晶体管结构的半导体衬底和在晶体管结构之间具有小于测试结构之间的间隔的测试结构。 第一迭代执行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有掺杂剂的第一浓度的第一掺杂外延层，并蚀刻第一掺杂外延层。 第二迭代进行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有高于第一浓度的掺杂剂的第二浓度的第二掺杂外延层，并蚀刻第二掺杂外延层。 第一个浓度导致超过晶体管结构的第一净增长率，而第二浓度导致比晶体管结构高出测试结构的较低的第二净增长率，导致模式负载减小。