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31.发明申请公开(公告)号：US20210250207A1
公开(公告)日：2021-08-12
申请号：US17252799
申请日：2019-06-14
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Charles Walter Boecker
IPC: H04L25/03
Abstract: A PAM-4 DFE receives an input signal distorted by inter-symbol interference (IS I) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of IS I offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the IS I offset for the immediate symbol.
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公开(公告)号：US11038725B2
公开(公告)日：2021-06-15
申请号：US16847793
申请日：2020-04-14
Applicant: Rambus Inc.
Inventor： Masum Hossain , Nhat Nguyen , Charles Walter Boecker
Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.
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公开(公告)号：US11038514B2
公开(公告)日：2021-06-15
申请号：US16885805
申请日：2020-05-28
Applicant: Rambus Inc.
Inventor： Masum Hossain , Kenneth C. Dyer , Nhat Nguyen , Shankar Tangirala
Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.
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公开(公告)号：US20210058278A1
公开(公告)日：2021-02-25
申请号：US17045769
申请日：2019-03-25
Applicant: Rambus Inc.
Inventor： Haidang Lin , Charles Walter Boecker , Masum Hossain
Abstract: A serial receiver combines continuous-time equalization, analog interleaving, and discrete-time gain for rapid, efficient data reception and quantization of a serial, continuous-time signal. A continuous-time equalizer equalizes a received signal. A number N of time-interleaved analog samplers sample the equalized continuous-time signal to provide N streams of analog samples transitioning at rate reduced by 1/N relative to the received signal. A set of N discrete-time variable-gain amplifiers amplify respective streams of analog samples. A quantizer then quantizes the amplified streams of analog samples to produce a digital signal.
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公开(公告)号：US10734971B2
公开(公告)日：2020-08-04
申请号：US16276677
申请日：2019-02-15
Applicant: Rambus Inc.
Inventor： Masum Hossain , Carl W. Werner
Abstract: Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.
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Patent Agency Ranking
公开(公告)号：US10263761B2
公开(公告)日：2019-04-16
申请号：US16032616
申请日：2018-07-11
Applicant: Rambus Inc.
Inventor： Masum Hossain , Brian Leibowitz , Jihong Ren
Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
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公开(公告)号：US10091036B1
公开(公告)日：2018-10-02
申请号：US15624556
申请日：2017-06-15
Applicant: Rambus Inc.
Inventor： Masum Hossain , Maruf H. Mohammad
Abstract: Methods and apparatuses for direct sequence detection can receive an input signal over a communication channel. Next, the input signal can be sampled based on a clock signal to obtain a sampled voltage. A set of reference voltages can be generated based on a main cursor, a set of pre-cursors, and a set of post-cursors associated with the communication channel. Each generated reference voltage in the set of reference voltages can correspond to a particular sequence of symbols. A sequence corresponding to the sampled voltage can be selected based on comparing the sampled voltage with the set of reference voltages.
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公开(公告)号：US20180069556A1
公开(公告)日：2018-03-08
申请号：US15644632
申请日：2017-07-07
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
CPC classification number: H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
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公开(公告)号：US09768947B2
公开(公告)日：2017-09-19
申请号：US15339342
申请日：2016-10-31
Applicant: Rambus Inc.
Inventor： Masum Hossain , Brian Leibowitz , Jihong Ren
CPC classification number: H04L7/0016 , H03L7/1974 , H03L7/235 , H04L7/033 , H04L27/0014 , H04L27/32 , H04L2027/0016 , H04L2027/0036 , H04L2027/0053 , H04L2027/0055 , H04L2027/0067
Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
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40.发明授权公开(公告)号：US09735792B2
公开(公告)日：2017-08-15
申请号：US14651571
申请日：2014-01-03
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Masum Hossain
CPC classification number: H03L7/24 , H03K3/0307 , H03K3/0315 , H03L1/00 , H03L7/06
Abstract: Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.
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