公开(公告)号：US06869862B2

公开(公告)日：2005-03-22

申请号：US10637288

申请日：2003-08-08

申请人： Brian K. Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

发明人： Brian K. Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L29/51 ,  H01I21/46 ,  H01L21/479 ,  H01I21/326 ,  H01I21/78

CPC分类号： H01L21/28176 ,  H01L21/3105 ,  H01L29/518

摘要： The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated circuit manufactured using the aforementioned method. In one aspect of the invention, the method for improving a physical property of a substrate includes subjecting the substrate to effects of a plasma process 830, wherein the substrate has a physical property defect value associated therewith subsequent to the plasma process. The method further includes exposing the substrate to an ultraviolet (UV) energy source 840 to improve the physical property defect value.

摘要翻译： 本发明提供一种提高基板的物理性能的方法，集成电路的制造方法以及使用上述方法制造的集成电路。 在本发明的一个方面，用于改善基板的物理性能的方法包括使基板受到等离子体工艺830的影响，其中基板在等离子体处理之后具有与其相关联的物理性能缺陷值。 该方法还包括将衬底暴露于紫外（UV）能量源840以改善物理性能缺陷值。

公开(公告)号：US08809141B2

公开(公告)日：2014-08-19

申请号：US11670192

申请日：2007-02-01

申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

IPC分类号： H01L29/739

CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7843 ,  Y10S438/954

摘要： A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

摘要翻译： 在晶体管栅极（40）和源极和漏极区域（70）之上形成硝酸氧化物层（110）。 所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。 将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。 在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。

公开(公告)号：US20090224296A1

公开(公告)日：2009-09-10

申请号：US12437004

申请日：2009-05-07

申请人： PR Chidambaram ,  Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

发明人： PR Chidambaram ,  Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

IPC分类号： H01L29/78

CPC分类号： H01L21/324 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/7833

摘要： A method (100) of forming semiconductor structures (202) including high-temperature processing steps (step 118), incorporates the use of a high-temperature nitride-oxide mask (220) over protected regions (214) of the device (202). The invention has application in many different embodiments, including but not limited to, the formation of recess, strained device regions (224).

摘要翻译： 形成包括高温处理步骤（步骤118）的半导体结构（202）的方法（100）包括在装置（202）的受保护区域（214）上使用高温氮氧化物掩模（220） 。 本发明应用于许多不同的实施例，包括但不限于形成凹陷，应变器件区域（224）。

公开(公告)号：US07129127B2

公开(公告)日：2006-10-31

申请号：US10950138

申请日：2004-09-24

申请人： Periannan Chidambaram ,  Srinivasan Chakravarthi ,  Haowen Bu ,  Rajesh Khamankar

发明人： Periannan Chidambaram ,  Srinivasan Chakravarthi ,  Haowen Bu ,  Rajesh Khamankar

IPC分类号： H01L21/8238

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap oxide layer is formed over the grown poly oxide layer (212). Offset spacers are formed adjacent to sidewalls of the gate electrodes (216). Extension regions are then formed (214) within the PMOS region and the NMOS region. Sidewall spacers are formed (218) adjacent to the sidewalls of the gate. electrodes. An n-type dopant is implanted into the NMOS region to form source/drain regions and a p-type dopant is implanted with an overdose amount into the PMOS region to form the source/drain regions within the PMOS region (220). A poly cap layer is formed over the device (222) and an anneal or other thermal process is performed (224) that causes the p-type dopant to diffuse into the nitride containing cap oxide layer and obtain a selected dopant profile having sufficient lateral abruptness.

公开(公告)号：US20050059228A1

公开(公告)日：2005-03-17

申请号：US10662850

申请日：2003-09-15

申请人： Haowen Bu ,  Shashank Ekbote ,  Rajesh Khamankar ,  Shaoping Tang ,  Freidoon Mehrad

发明人： Haowen Bu ,  Shashank Ekbote ,  Rajesh Khamankar ,  Shaoping Tang ,  Freidoon Mehrad

IPC分类号： H01L21/00 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/08 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845 ,  Y10S438/902

摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

公开(公告)号：US08021990B2

公开(公告)日：2011-09-20

申请号：US12421036

申请日：2009-04-09

申请人： Antonio L. P. Rotondaro ,  Luigi Colombo ,  Mark R Visokay ,  Rajesh Khamankar ,  Douglas E Mercer

发明人： Antonio L. P. Rotondaro ,  Luigi Colombo ,  Mark R Visokay ,  Rajesh Khamankar ,  Douglas E Mercer

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

摘要： A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.

摘要翻译： 一种MOSFET结构，包括在栅极材料沉积之前具有栅极电介质的氮化处理的硅酸盐栅极电介质。

公开(公告)号：US07601575B2

公开(公告)日：2009-10-13

申请号：US11072779

申请日：2005-03-04

申请人： Haowen Bu ,  Shashank Ekbote ,  Rajesh Khamankar ,  Shaoping Tang ,  Freidoon Mehrad

发明人： Haowen Bu ,  Shashank Ekbote ,  Rajesh Khamankar ,  Shaoping Tang ,  Freidoon Mehrad

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/44

CPC分类号： H01L29/0847 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845 ,  Y10S438/902

摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

摘要翻译： 本发明通过提供一种提高沟道电子迁移率而不会使PMOS晶体管器件基本上衰减的帽退火工艺来促进半导体器件的操作和制造。 该方法使用氧化物/氮化物复合帽来改变通道区域上的活性掺杂剂分布。 在退火过程中，掺杂剂在沟道区中迁移出Si / SiO 2，从而改变沟道区的掺杂物分布。 这种改变的形状通常改善了沟道迁移率，从而提高了晶体管的性能并允许更小的密度设计。

公开(公告)号：US20070207572A1

公开(公告)日：2007-09-06

申请号：US11745930

申请日：2007-05-08

申请人： Ajith Varghese ,  Husam Alshareef ,  Rajesh Khamankar

发明人： Ajith Varghese ,  Husam Alshareef ,  Rajesh Khamankar

IPC分类号： H01L21/82

CPC分类号： H01L21/28202 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

摘要： The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).

摘要翻译： 本发明提供了一种互补金属氧化物半导体（CMOS）器件及其制造方法，以及包括该互补金属氧化物半导体器件的集成电路。 在本发明的示例性实施例中，CMOS器件（100）包括具有第一栅极介电层（133）和位于第一栅极电极层（138）的p沟道金属氧化物半导体（PMOS）器件（120） 在衬底（110）上，其中第一栅极电介质层（133）具有位于其中的一定量的氮。 除了PMOS器件（120）之外，CMOS器件还包括具有第二栅极电介质层（173）和第二栅电极层（178）的n沟道金属氧化物半导体（NMOS）器件（160） 衬底（110），其中所述第二栅极电介质层（173）具有位于其中的不同量的氮。 因此，本发明允许对PMOS器件（120）和NMOS器件（160）的阈值电压进行单独调谐。

公开(公告)号：US07192894B2

公开(公告)日：2007-03-20

申请号：US10833419

申请日：2004-04-28

申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

IPC分类号： H01L21/31

CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7843 ,  Y10S438/954

摘要： A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

摘要翻译： 氮化硅层（110）形成在晶体管栅极（40）和源极和漏极区域（70）之上。 所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。 将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。 在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。

公开(公告)号：US20060043369A1

公开(公告)日：2006-03-02

申请号：US10927858

申请日：2004-08-27

申请人： Ajith Varghese ,  Husam Alshareef ,  Rajesh Khamankar

发明人： Ajith Varghese ,  Husam Alshareef ,  Rajesh Khamankar

IPC分类号： H01L29/76

CPC分类号： H01L21/28202 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

摘要： The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).

摘要翻译： 本发明提供了一种互补金属氧化物半导体（CMOS）器件及其制造方法，以及包括该互补金属氧化物半导体器件的集成电路。 在本发明的示例性实施例中，CMOS器件（100）包括具有第一栅极介电层（133）和位于第一栅极电极层（138）的p沟道金属氧化物半导体（PMOS）器件（120） 在衬底（110）上，其中第一栅极电介质层（133）具有位于其中的一定量的氮。 除了PMOS器件（120）之外，CMOS器件还包括具有第二栅极电介质层（173）和第二栅电极层（178）的n沟道金属氧化物半导体（NMOS）器件（160） 衬底（110），其中所述第二栅极电介质层（173）具有位于其中的不同量的氮。 因此，本发明允许对PMOS器件（120）和NMOS器件（160）的阈值电压进行单独调谐。