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    Systems and Methods for Temperature Insensitive Photonic Transmission
    31.
    发明申请
    Systems and Methods for Temperature Insensitive Photonic Transmission 审中-公开
    温度不敏感光子传输系统与方法

    公开(公告)号：US20140314406A1

    公开(公告)日：2014-10-23

    申请号：US14357386

    申请日：2012-11-30

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Dinesh Dilip Patil

    IPC: H04J14/02 ,  H04B10/079

    CPC classification number: H04J14/0221 ,  H04B10/07955 ,  H04B10/67 ,  H04B10/69 ,  H04J14/02 ,  H04J14/0256

    Abstract: A photonic communication system communicates M signals over a waveguide by modulating M wavelengths of light. N photonic rings at a receiver, where N is greater than M, are used to demodulate the M wavelengths. The modulated frequencies and resonant wavelengths of the receive rings are allowed to drift relative to one another. The number of receive rings is greater than the number of modulated frequency, and the number and optical characteristics of the receive rings are selected such that a subset of the receive rings effectively demodulates over the operational frequency range of the incoming light. The system tracks relative drift between the modulated wavelengths and the resonant wavelengths of the receiving rings and automatically selects the correct modulated signal or signals from among the receiving rings. The free spectral ranges and optical lengths of the receive rings are selected to reduce or minimize the number of receive rings required to span the optical bandwidth of the modulated light.

    Abstract translation: 光子通信系统通过调制M个波长的波长在波导上传送M个信号。 N个大于M的接收机的N个光子环用于解调M个波长。 允许接收环的调制频率和谐振波长相对于彼此漂移。 接收环的数量大于调制频率的数量，并且选择接收环的数量和光学特性，使得接收环的子集在入射光的工作频率范围内有效地解调。 该系统跟踪调制波长和接收环谐振波长之间的相对漂移，并自动从接收环中选择正确的调制信号或信号。 选择接收环的自由频谱范围和光学长度以减少或最小化跨越调制光的光学带宽所需的接收环的数量。

    Selectable-tap Equalizer
    32.
    发明申请
    Selectable-tap Equalizer 审中-公开
    可选择点击均衡器

    公开(公告)号：US20140286383A1

    公开(公告)日：2014-09-25

    申请号：US14145960

    申请日：2014-01-01

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Vladimir M. Stojanovic ,  Fred F. Chen

    IPC: H04B1/10 ,  H04L25/03

    CPC classification number: H04L25/03019 ,  H04B1/1081 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/03025 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885

    Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

    Abstract translation: 一种具有可选择抽头均衡器的信令电路。 信令电路包括缓冲器，选择电路和均衡电路。 缓冲器用于存储对应于在第一时间间隔期间在信令路径上发送的数据信号的多个数据值。 选择电路耦合到缓冲器，以根据选择值从多个数据值中选择数据值的子集。 均衡电路被耦合以从选择电路接收数据值的子集，并且适于根据数据值的子集来调整对应于在第二时间间隔期间在信令路径上发送的数据信号的信号电平。

    Low power edge and data sampling
    35.
    发明授权
    Low power edge and data sampling 有权

    公开(公告)号：US11258577B2

    公开(公告)日：2022-02-22

    申请号：US16914226

    申请日：2020-06-26

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe

    IPC: H04L7/033 ,  H04L7/00

    Abstract: An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

    Multi-mode clock multiplier
    36.
    发明授权
    Multi-mode clock multiplier 有权

    公开(公告)号：US10951218B2

    公开(公告)日：2021-03-16

    申请号：US16813156

    申请日：2020-03-09

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Masum Hossain

    IPC: H03L7/16 ,  H03L7/06 ,  H03L7/099 ,  H03K5/00 ,  H03K5/13 ,  H03K3/03 ,  H03K5/14 ,  H03L7/24

    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

    Selectable-tap Equalizer
    38.
    发明申请
    Selectable-tap Equalizer 审中-公开

    公开(公告)号：US20190342127A1

    公开(公告)日：2019-11-07

    申请号：US16432283

    申请日：2019-06-05

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Vladimir M. Stojanovic ,  Fred F. Chen

    IPC: H04L25/03 ,  H04L7/00 ,  H04L7/033 ,  H04B1/10

    Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

    Phase control block for managing multiple clock domains in systems with frequency offsets
    39.
    发明授权
    Phase control block for managing multiple clock domains in systems with frequency offsets 有权

    公开(公告)号：US10454667B2

    公开(公告)日：2019-10-22

    申请号：US15913764

    申请日：2018-03-06

    Applicant: Rambus Inc.

    Inventor： Hae-Chang Lee ,  Jared L. Zerbe ,  Carl William Werner

    IPC: H04L7/02 ,  H04L7/027 ,  H03L7/081 ,  H03L7/091 ,  H04L7/033 ,  H04L7/00

    Abstract: A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

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